From 5be75d5311695316f0d34448b98299cbe8b91ea5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 19 Aug 2019 08:41:50 +0300 Subject: AGESA,binaryPI: Replace use of __PRE_RAM__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/southbridge/amd/common/amd_pci_util.c | 3 --- src/southbridge/amd/common/amd_pci_util.h | 3 --- 2 files changed, 6 deletions(-) (limited to 'src/southbridge/amd/common') diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index f10a459bfd..b6d6308710 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -22,8 +22,6 @@ #include "amd_pci_int_defs.h" #include "amd_pci_int_types.h" -#ifndef __PRE_RAM__ - const struct pirq_struct * pirq_data_ptr = NULL; u32 pirq_data_size = 0; const u8 *intr_data_ptr = NULL; @@ -195,4 +193,3 @@ void write_pci_cfg_irqs(void) } /* for (dev = all_devices) */ printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index 9a4695e29a..0a3ce23a84 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -23,8 +23,6 @@ #define PCI_INTR_INDEX 0xc00 #define PCI_INTR_DATA 0xc01 -#ifndef __PRE_RAM__ - struct pirq_struct { u8 devfn; u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ @@ -39,6 +37,5 @@ u8 read_pci_int_idx(u8 index, int mode); void write_pci_int_idx(u8 index, int mode, u8 data); void write_pci_cfg_irqs(void); void write_pci_int_table (void); -#endif /* __PRE_RAM */ #endif /* AMD_PCI_UTIL_H */ -- cgit v1.2.3