From 399fcdd40d24e7f6fed80e5e1493c900be2b3772 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 23 Feb 2012 18:42:55 +0200 Subject: AMD southbridge: remove sp5100 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/679 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao Reviewed-by: Marc Jones --- src/southbridge/amd/sb700/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/amd/sb700/lpc.c') diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 3e596c240d..5dd7d696aa 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ -- cgit v1.2.3