From 83abd81c8acb3a53dfc125e248d9e5fd58f3e0f7 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 8 Jun 2015 19:35:06 -0500 Subject: cpu/amd: Add CC6 support This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Stefan Reinauer Reviewed-by: Ronald G. Minnich --- src/southbridge/amd/sb700/sm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/southbridge/amd/sb700/sm.c') diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index dc4b26fc14..04f4601883 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -123,7 +123,10 @@ static void sm_init(device_t dev) pci_write_config8(dev, 0x41, byte); byte = pm_ioread(0x61); - byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ + if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ + else + byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ pm_iowrite(0x61, byte); /* disable SMI */ -- cgit v1.2.3