From b01097e0fe03b7dc81eadd898ff380b57f291852 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Fri, 14 Dec 2012 15:58:15 +0800 Subject: USBDEBUG: Enable the EHCI in AMD Southbridge Since SB800, USB2.0 debug port is dev 0x12, func 2. Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55 Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-on: http://review.coreboot.org/1880 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin Reviewed-by: Stefan Reinauer Reviewed-by: Anton Kochkov Reviewed-by: Marc Jones --- src/southbridge/amd/sb800/enable_usbdebug.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/sb800/enable_usbdebug.c') diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 174b0f2aa5..158032e635 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -45,8 +45,12 @@ void set_debug_port(unsigned int port) void enable_usbdebug(unsigned int port) { - pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + + pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */ set_debug_port(port); } -- cgit v1.2.3