From 1eaaa0e446b88e0ad60c4b6f68a022a9184f1df8 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 14 Aug 2015 15:20:42 -0500 Subject: southbridge/amd/sr5650: Add MCFG ACPI table support As the southbridge largely controls the PCI[e] configuration space this patch moves the resource allocation from the northbridge to the southbridge when the extended configuration space region is enabled. Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Tested-by: Raptor Engineering Automated Test Stand --- src/southbridge/amd/sb800/lpc.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/southbridge/amd/sb800') diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 756a0c4200..18d4471545 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,6 @@ #include #include "sb800.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; -- cgit v1.2.3