From 13e4182119bcfcf09bdd9fa2b0cc5d09cd3550c2 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 27 Apr 2015 14:02:36 -0700 Subject: kbuild: automatically include southbridges This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge//Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/amd/Makefile.inc | 27 ---- src/southbridge/amd/agesa/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/pci.c | 2 +- src/southbridge/amd/amd8111/Makefile.inc | 4 + src/southbridge/amd/amd8131/Makefile.inc | 4 + src/southbridge/amd/amd8132/Makefile.inc | 4 + src/southbridge/amd/amd8151/Makefile.inc | 4 + src/southbridge/amd/amd_pci_util.c | 204 ------------------------------ src/southbridge/amd/amd_pci_util.h | 48 ------- src/southbridge/amd/cimx/Makefile.inc | 9 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/common/Makefile.inc | 7 + src/southbridge/amd/common/amd_pci_util.c | 204 ++++++++++++++++++++++++++++++ src/southbridge/amd/common/amd_pci_util.h | 48 +++++++ src/southbridge/amd/cs5535/Makefile.inc | 4 + src/southbridge/amd/cs5536/Makefile.inc | 6 +- src/southbridge/amd/pi/hudson/pci.c | 2 +- src/southbridge/amd/rs690/Makefile.inc | 4 + src/southbridge/amd/rs780/Makefile.inc | 4 + src/southbridge/amd/sb600/Makefile.inc | 4 + src/southbridge/amd/sb700/Makefile.inc | 4 + src/southbridge/amd/sb800/Makefile.inc | 4 + src/southbridge/amd/sr5650/Makefile.inc | 4 + 23 files changed, 319 insertions(+), 285 deletions(-) delete mode 100644 src/southbridge/amd/Makefile.inc delete mode 100644 src/southbridge/amd/amd_pci_util.c delete mode 100644 src/southbridge/amd/amd_pci_util.h create mode 100644 src/southbridge/amd/common/Makefile.inc create mode 100644 src/southbridge/amd/common/amd_pci_util.c create mode 100644 src/southbridge/amd/common/amd_pci_util.h (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc deleted file mode 100644 index cfb89d5a1d..0000000000 --- a/src/southbridge/amd/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fdd5d8047a..89d41b4a97 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 5858cd2ef7..cf1626d252 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -24,7 +24,7 @@ #include #include #include "hudson.h" -#include +#include #include diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc index c5b2688e0d..4c9ebaed88 100644 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ b/src/southbridge/amd/amd8111/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y) + ramstage-y += amd8111.c ramstage-y += usb.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += nic.c ramstage-y += pci.c ramstage-y += smbus.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc index ce96c9717b..8ec269157c 100644 --- a/src/southbridge/amd/amd8131/Makefile.inc +++ b/src/southbridge/amd/amd8131/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc index ce96c9717b..75dce39f54 100644 --- a/src/southbridge/amd/amd8132/Makefile.inc +++ b/src/southbridge/amd/amd8132/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc index dcb3c73543..07edf58085 100644 --- a/src/southbridge/amd/amd8151/Makefile.inc +++ b/src/southbridge/amd/amd8151/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y) + ramstage-y += agp3.c + +endif diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/amd_pci_util.c deleted file mode 100644 index 9f2cc5c1ee..0000000000 --- a/src/southbridge/amd/amd_pci_util.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "amd_pci_util.h" -#include -#include "amd_pci_int_defs.h" -#include "amd_pci_int_types.h" - -#ifndef __PRE_RAM__ - -const struct pirq_struct * pirq_data_ptr = NULL; -u32 pirq_data_size = 0; -const u8 * intr_data_ptr = NULL; -const u8 * picr_data_ptr = NULL; - -/* - * Read the FCH PCI_INTR registers 0xC00/0xC01 at a - * given index and a given PIC (0) or IOAPIC (1) mode - */ -u8 read_pci_int_idx(u8 index, int mode) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - return inb(PCI_INTR_DATA); -} - -/* - * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 - * at a given index and PIC (0) or IOAPIC (1) mode - */ -void write_pci_int_idx(u8 index, int mode, u8 data) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - outb(data, PCI_INTR_DATA); -} - -/* - * Write the FCH PCI_INTR registers 0xC00/0xC01 with values - * given in global variables intr_data and picr_data. - * These variables are defined in mainboard.c - */ -void write_pci_int_table (void) -{ - u8 byte; - - if(picr_data_ptr == NULL || intr_data_ptr == NULL){ - printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" - "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); - return; - } - - /* PIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 0)); - } - } - - /* APIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 1)); - } - } -} - -/* - * Function to write the PCI config space Interrupt - * registers based on the values given in PCI_INTR - * table at I/O port 0xC00/0xC01 - */ -void write_pci_cfg_irqs(void) -{ - device_t dev = NULL; /* Our current device to route IRQs to */ - device_t target_dev = NULL; /* The bridge that a device may be connected to */ - u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ - u16 target_pin = 0; /* Pin we will search our tables for */ - u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ - u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ - u16 devfn = 0; /* A PCI Device and Function number */ - u8 bridged_device = 0; /* This device is on a PCI bridge */ - u32 i = 0; - - if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'mainboard_pirq_data' structure does not exist\n"); - return; - } - - /* Populate the PCI cfg space header with the IRQ assignment */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - - for (dev = all_devices; dev; dev = dev->next) { - /* - * Step 1: Get the INT_PIN and device structure to look for in the - * PCI_INTR table pirq_data - */ - target_dev = NULL; - target_pin = get_pci_irq_pins(dev, &target_dev); - if (target_dev == NULL) - continue; - - if (target_pin < 1) - continue; - - /* Get the original INT_PIN for record keeping */ - int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); - if (int_pin < 1 || int_pin > 4) - continue; /* Device has invalid INT_PIN so skip it */ - - bus = target_dev->bus->secondary; - devfn = target_dev->path.pci.devfn; - - /* - * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR - * register (0xC00) index for this device - */ - pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ - for (i = 0; i < pirq_data_size; i++) { - if (pirq_data_ptr[i].devfn != devfn) - continue; - - /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ - pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; - printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); - break; - } - - /* - * Step 3: Make sure we got a valid index and use it to get - * the IRQ number from the PCI_INTR register table - */ - if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ - printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); - continue; - } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ - printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); - continue; - } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ - printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", - __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); - continue; - } - - /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ - int_line = read_pci_int_idx(pci_intr_idx, 0); - if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ - printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); - continue; - } - - /* - * Step 4: Program the INT_LINE register in this device's - * PCI config space with the IRQ number we found in step 3 - * and make it Level Triggered - */ - pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); - - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - - /* - * Step 5: Print out debug info and move on to next device - */ - printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", - int_pin, pin_to_str(int_pin)); - if (bridged_device) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - target_pin, pin_to_str(target_pin)); - printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); - } /* for (dev = all_devices) */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} -#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/amd_pci_util.h deleted file mode 100644 index 1d1e52baaf..0000000000 --- a/src/southbridge/amd/amd_pci_util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef AMD_PCI_UTIL_H -#define AMD_PCI_UTIL_H - -#include -#include "amd_pci_int_defs.h" - -/* FCH index/data registers */ -#define PCI_INTR_INDEX 0xc00 -#define PCI_INTR_DATA 0xc01 - -#ifndef __PRE_RAM__ - -struct pirq_struct { - u8 devfn; - u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ -}; - -extern const struct pirq_struct * pirq_data_ptr; -extern u32 pirq_data_size; -extern const u8 * intr_data_ptr; -extern const u8 * picr_data_ptr; - -u8 read_pci_int_idx(u8 index, int mode); -void write_pci_int_idx(u8 index, int mode, u8 data); -void write_pci_cfg_irqs(void); -void write_pci_int_table (void); -#endif /* __PRE_RAM */ - -#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index aacfc5844b..0754469b4e 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -16,10 +16,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 -romstage-y += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c -ramstage-y += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f4a7aa341a..ffa3290c8c 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -38,7 +38,7 @@ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" #include "fan.h" -#include +#include /*implement in mainboard.c*/ void set_pcie_reset(void); diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc new file mode 100644 index 0000000000..1f847cd0bb --- /dev/null +++ b/src/southbridge/amd/common/Makefile.inc @@ -0,0 +1,7 @@ +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c new file mode 100644 index 0000000000..9f2cc5c1ee --- /dev/null +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "amd_pci_util.h" +#include +#include "amd_pci_int_defs.h" +#include "amd_pci_int_types.h" + +#ifndef __PRE_RAM__ + +const struct pirq_struct * pirq_data_ptr = NULL; +u32 pirq_data_size = 0; +const u8 * intr_data_ptr = NULL; +const u8 * picr_data_ptr = NULL; + +/* + * Read the FCH PCI_INTR registers 0xC00/0xC01 at a + * given index and a given PIC (0) or IOAPIC (1) mode + */ +u8 read_pci_int_idx(u8 index, int mode) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + return inb(PCI_INTR_DATA); +} + +/* + * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 + * at a given index and PIC (0) or IOAPIC (1) mode + */ +void write_pci_int_idx(u8 index, int mode, u8 data) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + outb(data, PCI_INTR_DATA); +} + +/* + * Write the FCH PCI_INTR registers 0xC00/0xC01 with values + * given in global variables intr_data and picr_data. + * These variables are defined in mainboard.c + */ +void write_pci_int_table (void) +{ + u8 byte; + + if(picr_data_ptr == NULL || intr_data_ptr == NULL){ + printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" + "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); + return; + } + + /* PIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 0)); + } + } + + /* APIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 1)); + } + } +} + +/* + * Function to write the PCI config space Interrupt + * registers based on the values given in PCI_INTR + * table at I/O port 0xC00/0xC01 + */ +void write_pci_cfg_irqs(void) +{ + device_t dev = NULL; /* Our current device to route IRQs to */ + device_t target_dev = NULL; /* The bridge that a device may be connected to */ + u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ + u16 target_pin = 0; /* Pin we will search our tables for */ + u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ + u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ + u8 bus = 0; /* A PCI Device Bus number */ + u16 devfn = 0; /* A PCI Device and Function number */ + u8 bridged_device = 0; /* This device is on a PCI bridge */ + u32 i = 0; + + if (pirq_data_ptr == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'mainboard_pirq_data' structure does not exist\n"); + return; + } + + /* Populate the PCI cfg space header with the IRQ assignment */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + + for (dev = all_devices; dev; dev = dev->next) { + /* + * Step 1: Get the INT_PIN and device structure to look for in the + * PCI_INTR table pirq_data + */ + target_dev = NULL; + target_pin = get_pci_irq_pins(dev, &target_dev); + if (target_dev == NULL) + continue; + + if (target_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (int_pin < 1 || int_pin > 4) + continue; /* Device has invalid INT_PIN so skip it */ + + bus = target_dev->bus->secondary; + devfn = target_dev->path.pci.devfn; + + /* + * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR + * register (0xC00) index for this device + */ + pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ + for (i = 0; i < pirq_data_size; i++) { + if (pirq_data_ptr[i].devfn != devfn) + continue; + + /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ + pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; + printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); + break; + } + + /* + * Step 3: Make sure we got a valid index and use it to get + * the IRQ number from the PCI_INTR register table + */ + if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ + printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); + continue; + } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ + printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); + continue; + } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ + printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", + __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); + continue; + } + + /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ + int_line = read_pci_int_idx(pci_intr_idx, 0); + if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ + printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); + continue; + } + + /* + * Step 4: Program the INT_LINE register in this device's + * PCI config space with the IRQ number we found in step 3 + * and make it Level Triggered + */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); + + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + + /* + * Step 5: Print out debug info and move on to next device + */ + printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", + int_pin, pin_to_str(int_pin)); + if (bridged_device) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + target_pin, pin_to_str(target_pin)); + printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); + } /* for (dev = all_devices) */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} +#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h new file mode 100644 index 0000000000..1d1e52baaf --- /dev/null +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_UTIL_H +#define AMD_PCI_UTIL_H + +#include +#include "amd_pci_int_defs.h" + +/* FCH index/data registers */ +#define PCI_INTR_INDEX 0xc00 +#define PCI_INTR_DATA 0xc01 + +#ifndef __PRE_RAM__ + +struct pirq_struct { + u8 devfn; + u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ +}; + +extern const struct pirq_struct * pirq_data_ptr; +extern u32 pirq_data_size; +extern const u8 * intr_data_ptr; +extern const u8 * picr_data_ptr; + +u8 read_pci_int_idx(u8 index, int mode); +void write_pci_int_idx(u8 index, int mode, u8 data); +void write_pci_cfg_irqs(void); +void write_pci_int_table (void); +#endif /* __PRE_RAM */ + +#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc index 6f65e2e30d..3785cd4002 100644 --- a/src/southbridge/amd/cs5535/Makefile.inc +++ b/src/southbridge/amd/cs5535/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y) + ramstage-y += cs5535.c #ramstage-y += pci.c #ramstage-y += ide.c ramstage-y += chipsetinit.c + +endif diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index f36dcc54a6..2da076e14a 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -17,8 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) + ramstage-y += cs5536.c ramstage-y += ide.c ramstage-y += pirq.c ramstage-y += smbus.c -romstage-y += smbus.c \ No newline at end of file +romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 70e2c18854..5e71b4b242 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -24,7 +24,7 @@ #include #include #include "hudson.h" -#include +#include #include static void pci_init(struct device *dev) diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc index e0cf927812..c80ed9b611 100644 --- a/src/southbridge/amd/rs690/Makefile.inc +++ b/src/southbridge/amd/rs690/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y) + ramstage-y += rs690.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc index bf51d83e8f..1a8a17acac 100644 --- a/src/southbridge/amd/rs780/Makefile.inc +++ b/src/southbridge/amd/rs780/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y) + ramstage-y += rs780.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index 37fe57df1a..cd5bb6166d 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) + ramstage-y += sb600.c ramstage-y += usb.c ramstage-y += lpc.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 6e772fe5d1..5ec84312a3 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y) + ramstage-y += sb700.c ramstage-y += usb.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index d665af4639..fca4a984cb 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y) + ramstage-y += sb800.c ramstage-y += usb.c ramstage-y += lpc.c @@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc index 3c17be07c0..f695a112a6 100644 --- a/src/southbridge/amd/sr5650/Makefile.inc +++ b/src/southbridge/amd/sr5650/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y) + ramstage-y += sr5650.c ramstage-y += pcie.c ramstage-y += ht.c romstage-y += early_setup.c + +endif -- cgit v1.2.3