From a922b3195b77a3cc82bafad20dd3dfcfd2a61bc0 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Wed, 3 Jun 2009 03:15:05 +0000 Subject: Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming. Signed-off-by: Zheng Bao Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/rs690/rs690_pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c index 640fa75613..e0fc59d5cf 100644 --- a/src/southbridge/amd/rs690/rs690_pcie.c +++ b/src/southbridge/amd/rs690/rs690_pcie.c @@ -148,7 +148,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) /* waits until SB has trained to L0, poll for bit0-5 = 0x10 */ do { reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0); - reg &= 0x1f; /* remain LSB 5 bits */ + reg &= 0x3f; /* remain LSB [5:0] bits */ } while (LC_STATE_RECONFIG_GPPSB != reg); /* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ -- cgit v1.2.3