From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/broadcom/bcm21000/Makefile.inc | 2 +- src/southbridge/broadcom/bcm21000/bcm21000_pcie.c | 79 -------- src/southbridge/broadcom/bcm21000/pcie.c | 79 ++++++++ src/southbridge/broadcom/bcm5780/Makefile.inc | 6 +- src/southbridge/broadcom/bcm5780/bcm5780_nic.c | 64 ------ src/southbridge/broadcom/bcm5780/bcm5780_pcie.c | 60 ------ src/southbridge/broadcom/bcm5780/bcm5780_pcix.c | 52 ----- src/southbridge/broadcom/bcm5780/nic.c | 64 ++++++ src/southbridge/broadcom/bcm5780/pcie.c | 60 ++++++ src/southbridge/broadcom/bcm5780/pcix.c | 52 +++++ src/southbridge/broadcom/bcm5785/Makefile.inc | 12 +- .../broadcom/bcm5785/bcm5785_early_setup.c | 223 --------------------- .../broadcom/bcm5785/bcm5785_early_smbus.c | 61 ------ .../broadcom/bcm5785/bcm5785_enable_rom.c | 39 ---- src/southbridge/broadcom/bcm5785/bcm5785_ide.c | 67 ------- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c | 148 -------------- src/southbridge/broadcom/bcm5785/bcm5785_reset.c | 56 ------ src/southbridge/broadcom/bcm5785/bcm5785_sata.c | 100 --------- .../broadcom/bcm5785/bcm5785_sb_pci_main.c | 168 ---------------- src/southbridge/broadcom/bcm5785/bcm5785_smbus.h | 196 ------------------ src/southbridge/broadcom/bcm5785/bcm5785_usb.c | 64 ------ src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 223 +++++++++++++++++++++ src/southbridge/broadcom/bcm5785/early_smbus.c | 61 ++++++ src/southbridge/broadcom/bcm5785/enable_rom.c | 39 ++++ src/southbridge/broadcom/bcm5785/ide.c | 67 +++++++ src/southbridge/broadcom/bcm5785/lpc.c | 148 ++++++++++++++ src/southbridge/broadcom/bcm5785/reset.c | 56 ++++++ src/southbridge/broadcom/bcm5785/sata.c | 100 +++++++++ src/southbridge/broadcom/bcm5785/sb_pci_main.c | 168 ++++++++++++++++ src/southbridge/broadcom/bcm5785/smbus.h | 196 ++++++++++++++++++ src/southbridge/broadcom/bcm5785/usb.c | 64 ++++++ 32 files changed, 1388 insertions(+), 1388 deletions(-) delete mode 100644 src/southbridge/broadcom/bcm21000/bcm21000_pcie.c create mode 100644 src/southbridge/broadcom/bcm21000/pcie.c delete mode 100644 src/southbridge/broadcom/bcm5780/bcm5780_nic.c delete mode 100644 src/southbridge/broadcom/bcm5780/bcm5780_pcie.c delete mode 100644 src/southbridge/broadcom/bcm5780/bcm5780_pcix.c create mode 100644 src/southbridge/broadcom/bcm5780/nic.c create mode 100644 src/southbridge/broadcom/bcm5780/pcie.c create mode 100644 src/southbridge/broadcom/bcm5780/pcix.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_ide.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_lpc.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_reset.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_sata.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_smbus.h delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785_usb.c create mode 100644 src/southbridge/broadcom/bcm5785/early_setup.c create mode 100644 src/southbridge/broadcom/bcm5785/early_smbus.c create mode 100644 src/southbridge/broadcom/bcm5785/enable_rom.c create mode 100644 src/southbridge/broadcom/bcm5785/ide.c create mode 100644 src/southbridge/broadcom/bcm5785/lpc.c create mode 100644 src/southbridge/broadcom/bcm5785/reset.c create mode 100644 src/southbridge/broadcom/bcm5785/sata.c create mode 100644 src/southbridge/broadcom/bcm5785/sb_pci_main.c create mode 100644 src/southbridge/broadcom/bcm5785/smbus.h create mode 100644 src/southbridge/broadcom/bcm5785/usb.c (limited to 'src/southbridge/broadcom') diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc index 246be282e2..8e5ba7411b 100644 --- a/src/southbridge/broadcom/bcm21000/Makefile.inc +++ b/src/southbridge/broadcom/bcm21000/Makefile.inc @@ -1 +1 @@ -driver-y += bcm21000_pcie.c +driver-y += pcie.c diff --git a/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c b/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c deleted file mode 100644 index 72ee95b8cf..0000000000 --- a/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for - * University of Heidelberg. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - uint32_t dword; - uint32_t msicap; - - printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev)); - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - /* enable MSI on PCIE: */ - msicap = pci_read_config32(dev, 0xa0); - msicap |= (1<<16); /* enable MSI*/ - pci_write_config32(dev, 0xa0, msicap); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pcie_driver1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0, -}; - -static const struct pci_driver pcie_driver2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1, -}; - -static const struct pci_driver pcie_driver3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2, -}; diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c new file mode 100644 index 0000000000..72ee95b8cf --- /dev/null +++ b/src/southbridge/broadcom/bcm21000/pcie.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle for + * University of Heidelberg. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void pcie_init(struct device *dev) +{ + /* Enable pci error detecting */ + uint32_t dword; + uint32_t msicap; + + printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev)); + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (1<<30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + + /* enable MSI on PCIE: */ + msicap = pci_read_config32(dev, 0xa0); + msicap |= (1<<16); /* enable MSI*/ + pci_write_config32(dev, 0xa0, msicap); +} + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pcie_driver1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0, +}; + +static const struct pci_driver pcie_driver2 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1, +}; + +static const struct pci_driver pcie_driver3 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2, +}; diff --git a/src/southbridge/broadcom/bcm5780/Makefile.inc b/src/southbridge/broadcom/bcm5780/Makefile.inc index 55c6e11ec1..b8a1b96c27 100644 --- a/src/southbridge/broadcom/bcm5780/Makefile.inc +++ b/src/southbridge/broadcom/bcm5780/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += bcm5780_nic.c -driver-y += bcm5780_pcix.c -driver-y += bcm5780_pcie.c +driver-y += nic.c +driver-y += pcix.c +driver-y += pcie.c diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_nic.c b/src/southbridge/broadcom/bcm5780/bcm5780_nic.c deleted file mode 100644 index 387c402215..0000000000 --- a/src/southbridge/broadcom/bcm5780/bcm5780_nic.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -static void nic_init(struct device *dev) -{ -#if CONFIG_PCI_ROM_RUN == 1 - pci_dev_init(dev);// it will init option rom -#endif - -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_BROADCOM, - .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC, -}; - -static const struct pci_driver nic1_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_BROADCOM, - .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, -}; diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c b/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c deleted file mode 100644 index 786ad4f431..0000000000 --- a/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -static void pcie_init(struct device *dev) -{ - - /* Enable pci error detecting */ - uint32_t dword; - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, - -}; - -static const struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE, -}; diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c b/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c deleted file mode 100644 index e500542c33..0000000000 --- a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations ht_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0 , - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, - -}; - -static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB, -}; diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c new file mode 100644 index 0000000000..387c402215 --- /dev/null +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void nic_init(struct device *dev) +{ +#if CONFIG_PCI_ROM_RUN == 1 + pci_dev_init(dev);// it will init option rom +#endif + +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver nic_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC, +}; + +static const struct pci_driver nic1_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, +}; diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c new file mode 100644 index 0000000000..786ad4f431 --- /dev/null +++ b/src/southbridge/broadcom/bcm5780/pcie.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void pcie_init(struct device *dev) +{ + + /* Enable pci error detecting */ + uint32_t dword; + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (1<<30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + +} + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, + +}; + +static const struct pci_driver pcie_driver __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE, +}; diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c new file mode 100644 index 0000000000..e500542c33 --- /dev/null +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0 , + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, + +}; + +static const struct pci_driver ht_driver __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB, +}; diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc index e80ed35a34..9ad67ccf1f 100644 --- a/src/southbridge/broadcom/bcm5785/Makefile.inc +++ b/src/southbridge/broadcom/bcm5785/Makefile.inc @@ -1,7 +1,7 @@ driver-y += bcm5785.c -driver-y += bcm5785_usb.c -driver-y += bcm5785_lpc.c -driver-y += bcm5785_sb_pci_main.c -driver-y += bcm5785_ide.c -driver-y += bcm5785_sata.c -ramstage-y += bcm5785_reset.c +driver-y += usb.c +driver-y += lpc.c +driver-y += sb_pci_main.c +driver-y += ide.c +driver-y += sata.c +ramstage-y += reset.c diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c deleted file mode 100644 index e3edfd8635..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "bcm5785.h" - -static void bcm5785_enable_lpc(void) -{ - uint8_t byte; - device_t dev; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - /* LPC Control 0 */ - byte = pci_read_config8(dev, 0x44); - /* Serial 0 */ - byte |= (1<<6); - pci_write_config8(dev, 0x44, byte); - - /* LPC Control 4 */ - byte = pci_read_config8(dev, 0x48); - /* superio port 0x2e/4e enable */ - byte |=(1<<1)|(1<<0); - pci_write_config8(dev, 0x48, byte); -} - -static void bcm5785_enable_wdt_port_cf9(void) -{ - device_t dev; - uint32_t dword; - uint32_t dword_old; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - dword_old = pci_read_config32(dev, 0x4c); - dword = dword_old | (1<<4); //enable Timer Func - if(dword != dword_old ) { - pci_write_config32(dev, 0x4c, dword); - } - - dword_old = pci_read_config32(dev, 0x6c); - dword = dword_old | (1<<9); //unhide Timer Func in pci space - if(dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } - - dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); - - /* enable cf9 */ - pci_write_config8(dev, 0x40, (1<<2)); -} - -unsigned get_sbdn(unsigned bus) -{ - device_t dev; - - /* Find the device. - * There can only be one bcm5785 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(0x1166, 0x0036), - bus); - - return (dev>>15) & 0x1f; - -} - -#define SB_VFSMAF 0 - -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) -{ - //ACPI Decode Enable - outb(0x0e, 0xcd6); - outb((1<<3), 0xcd7); - - // set port to 0x2060 - outb(0x67, 0xcd6); - outb(0x60, 0xcd7); - outb(0x68, 0xcd6); - outb(0x20, 0xcd7); - - outb(0x69, 0xcd6); - outb(7, 0xcd7); - - outb(0x64, 0xcd6); - outb(9, 0xcd7); -} - -void ldtstop_sb(void) -{ - outb(1, 0x2060); -} - - -void hard_reset(void) -{ - bcm5785_enable_wdt_port_cf9(); - - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void soft_reset(void) -{ - bcm5785_enable_wdt_port_cf9(); - - set_bios_reset(); -#if 1 - /* link reset */ -// outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - -static void bcm5785_enable_msg(void) -{ - device_t dev; - uint32_t dword; - uint32_t dword_old; - uint8_t byte; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - byte = pci_read_config8(dev, 0x42); - byte = (1<<1); //enable a20 - pci_write_config8(dev, 0x42, byte); - - dword_old = pci_read_config32(dev, 0x6c); - // bit 5: enable A20 Message - // bit 4: enable interrupt messages - // bit 3: enable reset init message - // bit 2: enable keyboard init message - // bit 1: enable upsteam messages - // bit 0: enable shutdowm message to init generation - dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if(dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } -} - -static void bcm5785_early_setup(void) -{ - uint8_t byte; - uint32_t dword; - device_t dev; - -//F0 - // enable device on bcm5785 at first - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword = pci_read_config32(dev, 0x64); - dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable - dword |= (1<<8); // USB enable - dword |= /* (1<<27)|*/(1<<14); // IDE enable - pci_write_config32(dev, 0x64, dword); - - byte = pci_read_config8(dev, 0x84); - byte |= (1<<0); // SATA enable - pci_write_config8(dev, 0x84, byte); - -// WDT and cf9 for later in coreboot_ram to call hard_reset - bcm5785_enable_wdt_port_cf9(); - - bcm5785_enable_msg(); - - -// IDE related - //F0 - byte = pci_read_config8(dev, 0x4e); - byte |= (1<<4); //enable IDE ext regs - pci_write_config8(dev, 0x4e, byte); - - //F1 - dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); - byte = pci_read_config8(dev, 0x48); - byte &= ~1; // disable pri channel - pci_write_config8(dev, 0x48, byte); - pci_write_config8(dev, 0xb0, 0x01); - pci_write_config8(dev, 0xb2, 0x02); - byte = pci_read_config8(dev, 0x06); - byte |= (1<<4); // so b0, b2 can not be changed from now - pci_write_config8(dev, 0x06, byte); - byte = pci_read_config8(dev, 0x49); - byte |= 1; // enable second channel - pci_write_config8(dev, 0x49, byte); - - //F2 - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - byte = pci_read_config8(dev, 0x40); - byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable - pci_write_config8(dev, 0x40, byte); - - pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end - -// USB related - pci_write_config8(dev, 0x90, 0x40); - pci_write_config8(dev, 0x92, 0x06); - pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register - pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func - pci_write_config8(dev, 0xb4, 0x40); -} diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c deleted file mode 100644 index 3cc1292574..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "bcm5785_smbus.h" - -#define SMBUS_IO_BASE 0x1000 - -static void enable_smbus(void) -{ - device_t dev; - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - - print_debug("SMBus controller enabled\n"); - /* set smbus iobase */ - pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - /* Set smbus iospace enable */ - pci_write_config8(dev, 0xd2, 0x03); - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); -} - -static inline int smbus_recv_byte(unsigned device) -{ - return do_smbus_recv_byte(SMBUS_IO_BASE, device); -} - -static inline int smbus_send_byte(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); -} - -static inline int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); -} diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c b/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c deleted file mode 100644 index 1cd28498b9..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -static void bcm5785_enable_rom(void) -{ - u8 byte; - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, - PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); - - /* Set the 4MB enable bits. */ - byte = pci_read_config8(dev, 0x41); - byte |= 0x0e; - pci_write_config8(dev, 0x41, byte); -} diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c b/src/southbridge/broadcom/bcm5785/bcm5785_ide.c deleted file mode 100644 index a40094afde..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "bcm5785.h" - -static void bcm5785_ide_read_resources(device_t dev) -{ - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* BAR */ - pci_get_resource(dev, 0x64); - - compact_resources(dev); -} - -static void ide_init(struct device *dev) -{ -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations ide_ops = { - .read_resources = bcm5785_ide_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE, -}; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c deleted file mode 100644 index adf546245f..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "bcm5785.h" - -static void lpc_init(device_t dev) -{ - /* Initialize the real time clock */ - rtc_init(0); - - /* Initialize isa dma */ - isa_dma_init(); -} - -static void bcm5785_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -/** - * Enable resources for children devices. - * - * @param dev The device whos children's resources are to be enabled. - */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) -{ - struct bus *link; - uint32_t reg; - - reg = pci_read_config8(dev, 0x44); - - for (link = dev->link_list; link; link = link->next) { - device_t child; - for (child = link->children; child; child = child->sibling) { - if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for(res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long - if(!(res->flags & IORESOURCE_IO)) continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); - switch(base) { - case 0x60: //KBC - case 0x64: - reg |= (1<<29); - case 0x3f8: // COM1 - reg |= (1<<6); break; - case 0x2f8: // COM2 - reg |= (1<<7); break; - case 0x378: // Parallal 1 - reg |= (1<<0); break; - case 0x3f0: // FD0 - reg |= (1<<26); break; - case 0x220: // Aduio 0 - reg |= (1<<14); break; - case 0x300: // Midi 0 - reg |= (1<<18); break; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - - -} - -static void bcm5785_lpc_enable_resources(device_t dev) -{ - pci_dev_enable_resources(dev); - bcm5785_lpc_enable_childrens_resources(dev); -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = bcm5785_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = bcm5785_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC, -}; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c b/src/southbridge/broadcom/bcm5785/bcm5785_reset.c deleted file mode 100644 index a59b23992e..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c deleted file mode 100644 index 573e8475ce..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "bcm5785.h" - -static void sata_init(struct device *dev) -{ - uint8_t byte; - - u32 mmio; - struct resource *res; - u32 mmio_base; - int i; - - if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 - byte = pci_read_config8(dev, 0x78); - byte |= (1<<7); - pci_write_config8(dev, 0x78, byte); - - res = find_resource(dev, 0x24); - mmio_base = res->base; - mmio_base &= 0xfffffffc; - - write32(mmio_base + 0x10f0, 0x40000001); - write32(mmio_base + 0x8c, 0x00ff2007); - mdelay( 10 ); - write32(mmio_base + 0x8c, 0x78592009); - mdelay( 10 ); - write32(mmio_base + 0x8c, 0x00082004); - mdelay( 10 ); - write32(mmio_base + 0x8c, 0x00002004); - mdelay( 10 ); - - //init PHY - - printk(BIOS_DEBUG, "init PHY...\n"); - for(i=0; i<4; i++) { - mmio = res->base + 0x100 * i; - byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); - if(byte & 0x4) {// bit 2 is set - byte = read8(mmio+0x48); - write8(mmio + 0x48, byte | 1); - write8(mmio + 0x48, byte & (~1)); - byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); - } - } - } -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -// .enable = bcm5785_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA, -}; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c deleted file mode 100644 index 6c65fad4cf..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "bcm5785.h" -#include "bcm5785_smbus.h" - -#define NMI_OFF 0 - -static void sb_init(device_t dev) -{ - uint8_t byte; - uint8_t byte_old; - int nmi_option; - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if( byte != byte_old) { - outb(byte, 0x70); - } - - -} - -static void bcm5785_sb_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - /* Get Resource for SMBUS */ - pci_get_resource(dev, 0x90); - - compact_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - -} - -static int lsmbus_recv_byte(device_t dev) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(device_t dev, uint8_t val) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(device_t dev, uint8_t address) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations sb_ops = { - .read_resources = bcm5785_sb_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sb_init, - .scan_bus = scan_static_bus, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver sb_driver __pci_driver = { - .ops = &sb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, -}; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h b/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h deleted file mode 100644 index f6dfffa878..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { // ready now - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while(--loops); - return -2; // time out -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; // mask off reserved bits - if ( val & 0x1c) { - return -5; // error - } - if ( val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); // clear status - return 0; // - } - } while(--loops); - return -3; // timeout -} - -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - return byte; -} - -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - return 0; -} - -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - return byte; -} - -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - return 0; -} diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c b/src/southbridge/broadcom/bcm5785/bcm5785_usb.c deleted file mode 100644 index a16d6fe11b..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "bcm5785.h" - -static void usb_init(struct device *dev) -{ - uint32_t dword; - - dword = pci_read_config32(dev, 0x04); - dword |= (1<<2)|(1<<1)|(1<<0); - pci_write_config32(dev, 0x04, dword); - - pci_write_config8(dev, 0x41, 0x00); // Serversworks said - -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, -// .enable = bcm5785_enable, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB, -}; diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 40201c6072..f51fcd0ff9 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "bcm5785_enable_rom.c" +#include "enable_rom.c" static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c new file mode 100644 index 0000000000..e3edfd8635 --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -0,0 +1,223 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "bcm5785.h" + +static void bcm5785_enable_lpc(void) +{ + uint8_t byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + + /* LPC Control 0 */ + byte = pci_read_config8(dev, 0x44); + /* Serial 0 */ + byte |= (1<<6); + pci_write_config8(dev, 0x44, byte); + + /* LPC Control 4 */ + byte = pci_read_config8(dev, 0x48); + /* superio port 0x2e/4e enable */ + byte |=(1<<1)|(1<<0); + pci_write_config8(dev, 0x48, byte); +} + +static void bcm5785_enable_wdt_port_cf9(void) +{ + device_t dev; + uint32_t dword; + uint32_t dword_old; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + + dword_old = pci_read_config32(dev, 0x4c); + dword = dword_old | (1<<4); //enable Timer Func + if(dword != dword_old ) { + pci_write_config32(dev, 0x4c, dword); + } + + dword_old = pci_read_config32(dev, 0x6c); + dword = dword_old | (1<<9); //unhide Timer Func in pci space + if(dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } + + dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); + + /* enable cf9 */ + pci_write_config8(dev, 0x40, (1<<2)); +} + +unsigned get_sbdn(unsigned bus) +{ + device_t dev; + + /* Find the device. + * There can only be one bcm5785 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(0x1166, 0x0036), + bus); + + return (dev>>15) & 0x1f; + +} + +#define SB_VFSMAF 0 + +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +{ + //ACPI Decode Enable + outb(0x0e, 0xcd6); + outb((1<<3), 0xcd7); + + // set port to 0x2060 + outb(0x67, 0xcd6); + outb(0x60, 0xcd7); + outb(0x68, 0xcd6); + outb(0x20, 0xcd7); + + outb(0x69, 0xcd6); + outb(7, 0xcd7); + + outb(0x64, 0xcd6); + outb(9, 0xcd7); +} + +void ldtstop_sb(void) +{ + outb(1, 0x2060); +} + + +void hard_reset(void) +{ + bcm5785_enable_wdt_port_cf9(); + + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +void soft_reset(void) +{ + bcm5785_enable_wdt_port_cf9(); + + set_bios_reset(); +#if 1 + /* link reset */ +// outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +#endif +} + +static void bcm5785_enable_msg(void) +{ + device_t dev; + uint32_t dword; + uint32_t dword_old; + uint8_t byte; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + + byte = pci_read_config8(dev, 0x42); + byte = (1<<1); //enable a20 + pci_write_config8(dev, 0x42, byte); + + dword_old = pci_read_config32(dev, 0x6c); + // bit 5: enable A20 Message + // bit 4: enable interrupt messages + // bit 3: enable reset init message + // bit 2: enable keyboard init message + // bit 1: enable upsteam messages + // bit 0: enable shutdowm message to init generation + dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor + if(dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } +} + +static void bcm5785_early_setup(void) +{ + uint8_t byte; + uint32_t dword; + device_t dev; + +//F0 + // enable device on bcm5785 at first + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dword = pci_read_config32(dev, 0x64); + dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable + dword |= (1<<8); // USB enable + dword |= /* (1<<27)|*/(1<<14); // IDE enable + pci_write_config32(dev, 0x64, dword); + + byte = pci_read_config8(dev, 0x84); + byte |= (1<<0); // SATA enable + pci_write_config8(dev, 0x84, byte); + +// WDT and cf9 for later in coreboot_ram to call hard_reset + bcm5785_enable_wdt_port_cf9(); + + bcm5785_enable_msg(); + + +// IDE related + //F0 + byte = pci_read_config8(dev, 0x4e); + byte |= (1<<4); //enable IDE ext regs + pci_write_config8(dev, 0x4e, byte); + + //F1 + dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); + byte = pci_read_config8(dev, 0x48); + byte &= ~1; // disable pri channel + pci_write_config8(dev, 0x48, byte); + pci_write_config8(dev, 0xb0, 0x01); + pci_write_config8(dev, 0xb2, 0x02); + byte = pci_read_config8(dev, 0x06); + byte |= (1<<4); // so b0, b2 can not be changed from now + pci_write_config8(dev, 0x06, byte); + byte = pci_read_config8(dev, 0x49); + byte |= 1; // enable second channel + pci_write_config8(dev, 0x49, byte); + + //F2 + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + + byte = pci_read_config8(dev, 0x40); + byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable + pci_write_config8(dev, 0x40, byte); + + pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end + +// USB related + pci_write_config8(dev, 0x90, 0x40); + pci_write_config8(dev, 0x92, 0x06); + pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register + pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func + pci_write_config8(dev, 0xb4, 0x40); +} diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c new file mode 100644 index 0000000000..f235e58888 --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "smbus.h" + +#define SMBUS_IO_BASE 0x1000 + +static void enable_smbus(void) +{ + device_t dev; + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + } + + print_debug("SMBus controller enabled\n"); + /* set smbus iobase */ + pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); + /* Set smbus iospace enable */ + pci_write_config8(dev, 0xd2, 0x03); + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); +} + +static inline int smbus_recv_byte(unsigned device) +{ + return do_smbus_recv_byte(SMBUS_IO_BASE, device); +} + +static inline int smbus_send_byte(unsigned device, unsigned char val) +{ + return do_smbus_send_byte(SMBUS_IO_BASE, device, val); +} + +static inline int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} + +static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); +} diff --git a/src/southbridge/broadcom/bcm5785/enable_rom.c b/src/southbridge/broadcom/bcm5785/enable_rom.c new file mode 100644 index 0000000000..1cd28498b9 --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/enable_rom.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ +static void bcm5785_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, + PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); + + /* Set the 4MB enable bits. */ + byte = pci_read_config8(dev, 0x41); + byte |= 0x0e; + pci_write_config8(dev, 0x41, byte); +} diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c new file mode 100644 index 0000000000..a40094afde --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "bcm5785.h" + +static void bcm5785_ide_read_resources(device_t dev) +{ + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* BAR */ + pci_get_resource(dev, 0x64); + + compact_resources(dev); +} + +static void ide_init(struct device *dev) +{ +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations ide_ops = { + .read_resources = bcm5785_ide_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, +// .enable = bcm5785_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE, +}; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c new file mode 100644 index 0000000000..adf546245f --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bcm5785.h" + +static void lpc_init(device_t dev) +{ + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); +} + +static void bcm5785_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/** + * Enable resources for children devices. + * + * @param dev The device whos children's resources are to be enabled. + */ +static void bcm5785_lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + uint32_t reg; + + reg = pci_read_config8(dev, 0x44); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; child = child->sibling) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for(res = child->resource_list; res; res = res->next) { + unsigned long base, end; // don't need long long + if(!(res->flags & IORESOURCE_IO)) continue; + base = res->base; + end = resource_end(res); + printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); + switch(base) { + case 0x60: //KBC + case 0x64: + reg |= (1<<29); + case 0x3f8: // COM1 + reg |= (1<<6); break; + case 0x2f8: // COM2 + reg |= (1<<7); break; + case 0x378: // Parallal 1 + reg |= (1<<0); break; + case 0x3f0: // FD0 + reg |= (1<<26); break; + case 0x220: // Aduio 0 + reg |= (1<<14); break; + case 0x300: // Midi 0 + reg |= (1<<18); break; + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + + +} + +static void bcm5785_lpc_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + bcm5785_lpc_enable_childrens_resources(dev); +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations lpc_ops = { + .read_resources = bcm5785_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = bcm5785_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, +// .enable = bcm5785_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC, +}; diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c new file mode 100644 index 0000000000..a59b23992e --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) + +typedef unsigned device_t; + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); +} diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c new file mode 100644 index 0000000000..573e8475ce --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "bcm5785.h" + +static void sata_init(struct device *dev) +{ + uint8_t byte; + + u32 mmio; + struct resource *res; + u32 mmio_base; + int i; + + if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 + byte = pci_read_config8(dev, 0x78); + byte |= (1<<7); + pci_write_config8(dev, 0x78, byte); + + res = find_resource(dev, 0x24); + mmio_base = res->base; + mmio_base &= 0xfffffffc; + + write32(mmio_base + 0x10f0, 0x40000001); + write32(mmio_base + 0x8c, 0x00ff2007); + mdelay( 10 ); + write32(mmio_base + 0x8c, 0x78592009); + mdelay( 10 ); + write32(mmio_base + 0x8c, 0x00082004); + mdelay( 10 ); + write32(mmio_base + 0x8c, 0x00002004); + mdelay( 10 ); + + //init PHY + + printk(BIOS_DEBUG, "init PHY...\n"); + for(i=0; i<4; i++) { + mmio = res->base + 0x100 * i; + byte = read8(mmio + 0x40); + printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); + if(byte & 0x4) {// bit 2 is set + byte = read8(mmio+0x48); + write8(mmio + 0x48, byte | 1); + write8(mmio + 0x48, byte & (~1)); + byte = read8(mmio + 0x40); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); + } + } + } +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .enable = bcm5785_enable, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA, +}; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c new file mode 100644 index 0000000000..fe809c4974 --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bcm5785.h" +#include "smbus.h" + +#define NMI_OFF 0 + +static void sb_init(device_t dev) +{ + uint8_t byte; + uint8_t byte_old; + int nmi_option; + + /* Set up NMI on errors */ + byte = inb(0x70); // RTC70 + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + } else { + byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + } + if( byte != byte_old) { + outb(byte, 0x70); + } + + +} + +static void bcm5785_sb_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + /* Get Resource for SMBUS */ + pci_get_resource(dev, 0x90); + + compact_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + +} + +static int lsmbus_recv_byte(device_t dev) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_recv_byte(res->base, device); +} + +static int lsmbus_send_byte(device_t dev, uint8_t val) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_send_byte(res->base, device, val); +} + +static int lsmbus_read_byte(device_t dev, uint8_t address) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_write_byte(res->base, device, address, val); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x2c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations sb_ops = { + .read_resources = bcm5785_sb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sb_init, + .scan_bus = scan_static_bus, +// .enable = bcm5785_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; + +static const struct pci_driver sb_driver __pci_driver = { + .ops = &sb_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, +}; diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h new file mode 100644 index 0000000000..f6dfffa878 --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { // ready now + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while(--loops); + return -2; // time out +} + +static int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; // mask off reserved bits + if ( val & 0x1c) { + return -5; // error + } + if ( val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); // clear status + return 0; // + } + } while(--loops); + return -3; // timeout +} + +static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +{ + uint8_t byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + return byte; +} + +static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +{ + uint8_t byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } + + return 0; +} + +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + uint8_t byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + return byte; +} + +static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +{ + uint8_t byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } + + return 0; +} diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c new file mode 100644 index 0000000000..a16d6fe11b --- /dev/null +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "bcm5785.h" + +static void usb_init(struct device *dev) +{ + uint32_t dword; + + dword = pci_read_config32(dev, 0x04); + dword |= (1<<2)|(1<<1)|(1<<0); + pci_write_config32(dev, 0x04, dword); + + pci_write_config8(dev, 0x41, 0x00); // Serversworks said + +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, +// .enable = bcm5785_enable, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver usb_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB, +}; -- cgit v1.2.3