From d4b278c02c1da92219ebeb34204b9768934aeca3 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Wed, 4 Oct 2006 20:46:15 +0000 Subject: AMD Rev F support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- .../broadcom/bcm5785/bcm5785_early_setup.c | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'src/southbridge/broadcom') diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c index ab94327481..8167691dea 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c @@ -71,6 +71,48 @@ static void bcm5785_enable_wdt_port_cf9(void) pci_write_config8(dev, 0x40, (1<<2)); } +static unsigned get_sbdn(unsigned bus) +{ + device_t dev; + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(0x1166, 0x0036), + bus); + + return (dev>>15) & 0x1f; + +} + +#define SB_VFSMAF 0 + +static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +{ + //ACPI Decode Enable + outb(0x0e, 0xcd6); + outb((1<<3), 0xcd7); + + // set port to 0x2060 + outb(0x67, 0xcd6); + outb(0x60, 0xcd7); + outb(0x68, 0xcd6); + outb(0x20, 0xcd7); + + outb(0x69, 0xcd6); + outb(7, 0xcd7); + + outb(0x64, 0xcd6); + outb(9, 0xcd7); +} + +static void ldtstop_sb(void) +{ + outb(1, 0x2060); +} + + static void hard_reset(void) { bcm5785_enable_wdt_port_cf9(); -- cgit v1.2.3