From 45022ae056cdbf58429b77daf2da176306312801 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 1 Oct 2018 19:17:11 +0200 Subject: intel: Use CF9 reset (part 1) Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/intel/bd82x6x/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/Makefile.inc') diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index ea8e96c338..d8730dfdd3 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += me_status.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c @@ -39,7 +38,6 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c -- cgit v1.2.3