From 729c0695e5e93d7f7e48ddd72787769ff62cd8b9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:50:44 +0200 Subject: sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/early_usb_mrc.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/early_usb_mrc.c') diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 0896a4d966..f60cc0b706 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -18,19 +18,14 @@ void enable_usb_bar(void) { pci_devfn_t usb0 = PCH_EHCI1_DEV; pci_devfn_t usb1 = PCH_EHCI2_DEV; - u32 cmd; /* USB Controller 1 */ pci_write_config32(usb0, PCI_BASE_ADDRESS_0, PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_or_config16(usb0, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, PCH_EHCI2_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); + pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -- cgit v1.2.3