From c803f65206188ca74526054c54bce4f405a55850 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 7 Jun 2020 22:09:01 +0200 Subject: sb/intel/bd82x6x: Use PCI bitwise ops Some cases could not be factored out while keeping reproducibility. Also mark some potential bugs with a FIXME comment, since fixing them while also keeping the binary unchanged is pretty much impossible. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/southbridge/intel/bd82x6x/lpc.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/lpc.c') diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bdaca57829..c0f62bd7fb 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -417,22 +417,15 @@ static void pch_set_acpi_mode(void) static void pch_disable_smm_only_flashing(struct device *dev) { - u8 reg8; - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); + + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); } static void pch_fixups(struct device *dev) { - u8 gen_pmcon_2; - /* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); - gen_pmcon_2 |= (1 << 7); - pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); /* * Enable DMI ASPM in the PCH -- cgit v1.2.3