From 708f731fd76c3698b598b35469ae2fb20f08ae51 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 10 Jul 2012 15:15:41 -0700 Subject: ME: Move ME v8 lockdown to finalize step The ME device was being sent EOP and the PCI device hidden during coreboot so it was not available in the SMI finalize step. This also flips the PCI vendor/device dword around for the match. Boot on Panther Point with serial and SMI debugging enabled and see that ME EOP message is sent and the device is hidden at end of U-boot and before the kernel loads. Finalizing Coreboot SMI# #0 ME: mkhi_end_of_post ME: END OF POST message successful (0) PM1_STS: TMROF PM1_EN: 120 Starting kernel ... Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/1338 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/bd82x6x/me.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/me.c') diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 25b88b98bb..464d0fde0e 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -535,10 +535,10 @@ void intel_me_finalize_smm(void) { u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { - case 0x80861c3a: + case 0x1c3a8086: intel_me7_finalize_smm(); break; - case 0x80861e3a: + case 0x1e3a8086: intel_me8_finalize_smm(); break; default: -- cgit v1.2.3