From 59aef5c79e7ae85854a88db4803334617d7b83fd Mon Sep 17 00:00:00 2001
From: Nicolas Reinecke <nr@das-labor.org>
Date: Thu, 16 Apr 2015 23:25:00 +0200
Subject: southbrige/intel/bd82x6x: add XHCI overcurrent map config

Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9449
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/southbridge/intel/bd82x6x/pch.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/southbridge/intel/bd82x6x/pch.h')

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7b52ebc3e3..4ec29035d1 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -449,6 +449,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define USBOCM2		0x35a4	/* 32bit */
 
 /* XHCI USB 3.0 */
+#define XOCM		0xc0	/* 32bit */
 #define XUSB2PRM	0xd4	/* 32bit */
 #define USB3PRM		0xdc	/* 32bit */
 
-- 
cgit v1.2.3