From b17a0f592c4d725958539a089df0f9b22ac2d7e2 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Mon, 25 Nov 2019 23:26:36 +0100
Subject: sb/intel/*: Remove romcc guards

These platforms now use a GCC compiled bootblock.

Change-Id: I9a0139f497fe84860664195ed6584f90daecec16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/bd82x6x/pch.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src/southbridge/intel/bd82x6x/pch.h')

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 127fb61cce..089d4586bf 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -90,10 +90,8 @@ struct southbridge_usb_port
 	int oc_pin;
 };
 
-#ifndef __ROMCC__
 void pch_enable(struct device *dev);
 extern const struct southbridge_usb_port mainboard_usb_ports[14];
-#endif
 
 void early_usb_init(const struct southbridge_usb_port *portmap);
 
-- 
cgit v1.2.3