From 580e7223bb617cfa14bf24e48bb39bac47c4e8e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 19 Mar 2015 21:04:23 +0200 Subject: devicetree: Change scan_bus() prototype in device ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The input/output value max is no longer used for tracking the bus enumeration sequence, everything is handled in the context of devicetree bus objects. Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8541 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Timothy Pearson Reviewed-by: Patrick Georgi --- src/southbridge/intel/bd82x6x/pcie.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'src/southbridge/intel/bd82x6x') diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 42a8578b1d..1b8ac76126 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -273,13 +273,12 @@ static void pch_pcie_enable(device_t dev) pch_pcie_pm_early(dev); } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_bd82x6x_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); @@ -287,8 +286,6 @@ static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) /* Late Power Management init after bridge device enumeration */ pch_pcie_pm_late(dev); - - return ret; } static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) -- cgit v1.2.3