From 63626b1a4a31588995ff6f0ba42952b6086cbded Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Fri, 30 Nov 2018 22:53:50 +1300 Subject: sb/intel/common: Create a common PCH finalise implementation The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/common/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/southbridge/intel/common/Makefile.inc') diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b87354c5e8..1a509b16a4 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -54,6 +54,8 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c + romstage-y += rtc.c ramstage-y += rtc.c postcar-y += rtc.c -- cgit v1.2.3