From bddef0dae73676c44364cd9d53813144ce42198a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Sep 2017 12:21:07 +0200 Subject: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI This introduces a Kconfig option to include common Intel SPI code. Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/common/Kconfig | 4 ++++ src/southbridge/intel/common/Makefile.inc | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'src/southbridge/intel/common') diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 304ecbfba3..6ce6b33579 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -8,6 +8,10 @@ config SOUTHBRIDGE_INTEL_COMMON_SMBUS def_bool n select HAVE_DEBUG_SMBUS +config SOUTHBRIDGE_INTEL_COMMON_SPI + def_bool n + select SPI_FLASH + config HAVE_INTEL_CHIPSET_LOCKDOWN def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5810394bcb..0128505d66 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -28,4 +28,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +endif + endif -- cgit v1.2.3