From e7377556cc33b10fdba6d956ac83d823478f5eb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 21 Jun 2018 16:20:55 +0300 Subject: device: Use pcidev_path_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/southbridge/intel/fsp_rangeley/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/fsp_rangeley') diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index fbdc6e320b..96ddea5be6 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -34,7 +34,7 @@ typedef struct southbridge_intel_fsp_rangeley_config config_t; void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = dev_find_slot(0, SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(SOC_LPC_DEVFN); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = lpcdev->chip_info; -- cgit v1.2.3