From 12b121cdb450d96309dd96b2ccc25fc5501d2250 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 18 Aug 2019 16:33:39 +0300 Subject: southbridge/intel: Tidy up preprocessor and headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82371eb/i82371eb.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'src/southbridge/intel/i82371eb/i82371eb.h') diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 5e0ff3f418..77931cb20c 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -17,18 +17,22 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#if !defined(__PRE_RAM__) -#include -#include "chip.h" +#if !defined(__ACPI__) +#ifndef __ROMCC__ +#include void i82371eb_enable(struct device *dev); +#endif + void i82371eb_hard_reset(void); -#else + void enable_smbus(void); -int smbus_read_byte(u8 device, u8 address); void enable_pm(void); + +#if ENV_ROMSTAGE +int smbus_read_byte(u8 device, u8 address); #endif + #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the -- cgit v1.2.3