From 7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:29:38 -0600 Subject: southbridge/intel: add IS_ENABLED() around Kconfig symbol references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i82371eb/isa.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/southbridge/intel/i82371eb/isa.c') diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bd0e964378..2bab05cb15 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -28,7 +28,7 @@ #endif #include "i82371eb.h" -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) static void enable_intel_82093aa_ioapic(void) { u16 reg16; @@ -84,7 +84,7 @@ static void isa_init(struct device *dev) /* Initialize ISA DMA. */ isa_dma_init(); -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -115,7 +115,7 @@ static void sb_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; -- cgit v1.2.3