From 1bcd7fcb6199528fc82685e161d6b39f273a1962 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:20:04 +0200 Subject: src/southbridge: Capitalize CPU, RAM and ROM Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Tobias Diedrich --- src/southbridge/intel/i82371eb/fadt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/i82371eb') diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 9d0e15c976..b77ed4a292 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -78,11 +78,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ - fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */ + fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ fadt->flush_stride = 0; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc cmos ram offset */ + fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */ fadt->mon_alrm = 0x0; /* not supported */ fadt->century = 0x0; /* not supported */ /* -- cgit v1.2.3