From c4e052cd5089019dc67b4fa176bca6d8d19de30d Mon Sep 17 00:00:00 2001 From: Ed Swierk Date: Tue, 1 Apr 2008 02:36:59 +0000 Subject: The early init code of several Intel southbridge chipsets calls pci_locate_device() to locate the SMBus controller and LPC bridge devices on the PCI bus. Since these devices are always located at a fixed PCI bus:device:function, the code can be simplified by hardcoding the devices. Signed-off-by: Ed Swierk Acked-by: Corey Osgood git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/southbridge/intel/i82801dbm') diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c b/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c index 39bd971fbd..a85c08b9bb 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c +++ b/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c @@ -21,12 +21,8 @@ static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24c3), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } - + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_debug("SMBus controller enabled\r\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); -- cgit v1.2.3