From 1234925ad77aa888fb28034251b950e1bc2fd480 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 27 Apr 2020 05:08:26 +0200 Subject: sb/intel/i82801gx: Fix 16-bit read/write PCI_COMMAND register Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40741 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/i82801gx.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'src/southbridge/intel/i82801gx/i82801gx.c') diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 1a5366fe87..eae16db3d3 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -54,23 +54,21 @@ static void ich_hide_devfn(unsigned int devfn) void i82801gx_enable(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ ich_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) { printk(BIOS_DEBUG, "Set SATA mode early\n"); -- cgit v1.2.3