From b451df2f400ba12fff440247330f8b57a93034bd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 Aug 2017 20:59:09 +0200 Subject: mb/*/*/romstage.c: Clean up targets with i82801gx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i82801gx/i82801gx.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/southbridge/intel/i82801gx/i82801gx.h') diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b3c1b48ec2..df744fc73c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -125,6 +125,11 @@ int southbridge_detect_s3_resume(void); #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ +#define GEN1_DEC 0x84 +#define GEN2_DEC 0x88 +#define GEN3_DEC 0x8c +#define GEN4_DEC 0x90 + /* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -- cgit v1.2.3