From c274be5fc4a608f7de1dfa7c28a0db4412855da1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 1 Jun 2020 20:21:26 +0200 Subject: x4x/i82801jx: Use common code for early SMBus The early SMBus code for this chipset was not checking the vendor ID before. It is assumed that adding this check does not pose a problem. Change-Id: I0c36c8cd8aca8db860b1edafd29d4f2dbaa2c822 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42003 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/early_smbus.c | 29 ---------------------------- 1 file changed, 29 deletions(-) delete mode 100644 src/southbridge/intel/i82801jx/early_smbus.c (limited to 'src/southbridge/intel/i82801jx/early_smbus.c') diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c deleted file mode 100644 index c4b82bbf9e..0000000000 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include "i82801jx.h" - -uintptr_t smbus_base(void) -{ - return CONFIG_FIXED_SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} -- cgit v1.2.3