From 2048cb43863f014fedc4ff44233d49410f0cee5e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 8 Jun 2020 02:09:33 +0200 Subject: sb/intel/i82801jx: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/smbus.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/southbridge/intel/i82801jx/smbus.c') diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 4f45d8a5cb..32b64b89df 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -11,12 +11,8 @@ static void pch_smbus_init(struct device *dev) { - u16 reg16; - /* Enable clock gating */ - reg16 = pci_read_config16(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); - pci_write_config16(dev, 0x80, reg16); + pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); } static int lsmbus_read_byte(struct device *dev, u8 address) -- cgit v1.2.3