From 7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:29:38 -0600 Subject: southbridge/intel: add IS_ENABLED() around Kconfig symbol references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/lynxpoint/me_9.x.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/me_9.x.c') diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 355db4b6e1..c393feb377 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -37,7 +37,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include #include #endif @@ -59,7 +59,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); static u32 *mei_base_address; void intel_me_mbp_clear(device_t dev); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -519,7 +519,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) #endif /* CONFIG_DEBUG_INTEL_ME */ #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -579,7 +579,7 @@ void intel_me_finalize_smm(void) if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if CONFIG_ME_MBP_CLEAR_LATE +#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); #endif @@ -707,7 +707,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -796,7 +796,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -835,7 +835,7 @@ static void intel_me_init(device_t dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) me_print_fwcaps(mbp_data.fw_capabilities); #endif @@ -991,7 +991,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) host.interrupt_generate = 1; write_host_csr(&host); -#if !CONFIG_ME_MBP_CLEAR_LATE +#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for the mbp_cleared indicator. */ intel_me_mbp_clear(dev); #endif @@ -1000,7 +1000,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } -- cgit v1.2.3