From da5f5094f04ce8a5a15f89ce39e291cf723773fd Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 13 Jul 2016 23:23:16 -0500 Subject: southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15676 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- src/southbridge/intel/lynxpoint/usb_ehci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/usb_ehci.c') diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 098a63e865..e2486cfa02 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -71,8 +71,8 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) pci_cmd = pci_read_config32(dev, PCI_COMMAND); switch (slp_typ) { - case SLP_TYP_S4: - case SLP_TYP_S5: + case ACPI_S4: + case ACPI_S5: /* Check if controller is in D3 power state */ pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS); if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { -- cgit v1.2.3