From 0d9b360b42d39d211d62f0c213aae9e7cf3f2924 Mon Sep 17 00:00:00 2001 From: Ryan Salsamendi Date: Fri, 30 Jun 2017 17:15:57 -0700 Subject: southbridge/intel/lynxpoint: Fix undefined behavior MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Signed-off-by: Ryan Salsamendi Reviewed-on: https://review.coreboot.org/20443 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paul Menzel --- src/southbridge/intel/lynxpoint/usb_xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/usb_xhci.c') diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 0acf35ff7c..28e6521598 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -342,13 +342,13 @@ static void usb_xhci_init(device_t dev) /* D20:F0:44h[31] = 1 (Access Control Bit) */ reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x40, reg32); if (acpi_is_wakeup_s3()) { -- cgit v1.2.3