From 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 3 May 2016 15:53:33 -0700 Subject: intel/sch: Merge northbridge and southbridge in src/soc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Vladimir Serbinenko --- src/southbridge/intel/sch/chip.h | 34 ---------------------------------- 1 file changed, 34 deletions(-) delete mode 100644 src/southbridge/intel/sch/chip.h (limited to 'src/southbridge/intel/sch/chip.h') diff --git a/src/southbridge/intel/sch/chip.h b/src/southbridge/intel/sch/chip.h deleted file mode 100644 index 0c1c91ead6..0000000000 --- a/src/southbridge/intel/sch/chip.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_SCH_CHIP_H -#define SOUTHBRIDGE_INTEL_SCH_CHIP_H - -struct southbridge_intel_sch_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; -}; - -#endif -- cgit v1.2.3