From 1b85692fc4247659a188cba577ba8c35aa373fbd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 15:30:48 +0100 Subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bus Master is not required and reference code does not set it. Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore. Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner --- src/southbridge/intel/lynxpoint/sata.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 510440b76a..e1a2fa5a57 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -41,9 +41,8 @@ static void sata_init(struct device *dev) /* SATA configuration */ - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); -- cgit v1.2.3