From 49fdf3f957869dab82b46d6548f73ceab909132b Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 26 Nov 2015 15:58:12 -0700 Subject: intel/fsp_rangeley: change non-existent config options to #defines Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/12552 Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 22edf50930..696a81ae65 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -30,7 +30,7 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_PMIO) +#ifdef ACPI_INCLUDE_PMIO // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) @@ -77,7 +77,7 @@ Scope(\) } #endif -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_GPIO) +#ifdef ACPI_INCLUDE_GPIO // GPIO IO mapped registers (0x1f.0 reg 0x48.l) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve) -- cgit v1.2.3