From d1a0c5770803e45dabecf6094fccb9895ea76d10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 30 Jul 2017 11:37:14 +0300 Subject: usbdebug: Consolidate EHCI_BAR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/southbridge/intel/common/usb_debug.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index eeac6d92dc..e1cd6575d0 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -63,10 +63,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) /* Bail out. No console to complain in. */ if (!dev) return; - - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, base); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } -- cgit v1.2.3