From f503b60bb9f374741d6d262c4db04e4a4c3aaa0b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 16 Sep 2019 21:00:22 +0200 Subject: sb/intel/ibexpeak: Add CIR initialization This properly sets up the chipset initialization registers, instead of replaying an RCBA dump. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI. TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/ibexpeak/Makefile.inc | 1 + src/southbridge/intel/ibexpeak/early_cir.c | 92 +++++++++++++++++++++++++++++ src/southbridge/intel/ibexpeak/pch.h | 19 ++++++ 3 files changed, 112 insertions(+) create mode 100644 src/southbridge/intel/ibexpeak/early_cir.c (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f3ae..97565d6bec 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c endif diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c new file mode 100644 index 0000000000..004823530b --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "pch.h" + +/* This sets up magic Chipset Initialization Registers */ +void pch_setup_cir(int chipset_type) +{ + printk(BIOS_DEBUG, "Setting up Chipset Initialization Registers (CIR)\n"); + + uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + struct cpuinfo_x86 c; + uint32_t cir22; + + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 0xfb); + + RCBA32_OR(GCS, 0x40); /* FERR# MUX enable */ + + RCBA8(0x3430) |= 0xfc; + + RCBA32(CIR7) = 0xf; + + RCBA32(CIR9) = 0; + + switch (lpc_id) { + case 0x3b01: + case 0x3b03: + case 0x3b05: + case 0x3b07: + case 0x3b09: + case 0x3b0b: + case 0x3b0d: + case 0x3b0f: + RCBA32_AND_OR(CIR6, 0xff1fff7f, 0x600000); + break; + } + + RCBA32_OR(0x3310, 0x31); + + /* Intel 5 Series Chipset and Intel 3400 Series Chipset + External Design Specification (EDS) 13.8.1.1 */ + if (chipset_type == NEHALEM_DESKTOP) + pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); + + pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); + + RCBA32(CIR8) = 0x4000000; + pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300); + RCBA32(0x3318) = 0x1020000; /* undocumented */ + get_fms(&c, cpuid_eax(1)); + if (c.x86_model == 0x1e) { + /* Lynnfield/Clarksfield */ + RCBA32(CIR13) = 0xfffff; + RCBA32(CIR14) = 0x61080; + RCBA32(CIR16) = 0x7f8f9f80; + RCBA32(CIR18) = 0x3900; + RCBA32(CIR19) = 0x20002; + RCBA32(CIR20) = 0x44b00; + RCBA32(CIR21) = 0x02000; + cir22 = 0x20000; + } else if (c.x86_model == 0x1f || c.x86_model == 0x25) { + /* Auburndale/Havendale + Arrandale/Clarkdale */ + RCBA32(CIR10) = 0xfff80; + RCBA32(CIR15) = 0x7f8f9fff; + RCBA32(CIR17) = 0x2900; + RCBA32(CIR19) = 0x10001; + RCBA32(CIR20) = 0x1004b; + RCBA32(CIR21) = 0x8; + cir22 = 0x10000; + } else { + die("unsupported CPU model: %x!\n", c.x86_model); + } + + /* EDS, 10.1.77: Program this register after all registers in the + 3330-33D3 range and D31:F0:A9h are already programmed */ + RCBA32(CIR22) = cir22; +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index f7b29291db..f0e469a3ac 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@ int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void pch_setup_cir(int chipset_type); #ifndef __ROMCC__ #include @@ -100,6 +101,9 @@ void pch_enable(struct device *dev); #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) +#define CIR4 0xa9 +#define PMIR 0xac + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) @@ -349,6 +353,21 @@ void pch_enable(struct device *dev); #define SOFT_RESET_DATA 0x38f8 #define PRSTS 0x3310 +#define CIR6 0x2024 +#define CIR7 0x3314 +#define CIR8 0x3324 +#define CIR9 0x3330 +#define CIR10 0x3340 +#define CIR13 0x3350 +#define CIR14 0x3368 +#define CIR15 0x3378 +#define CIR16 0x3388 +#define CIR17 0x33a0 +#define CIR18 0x33a8 +#define CIR19 0x33c0 +#define CIR20 0x33cc +#define CIR21 0x33d0 +#define CIR22 0x33d4 #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ -- cgit v1.2.3