From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/nvidia/ck804/Makefile.inc | 30 +- src/southbridge/nvidia/ck804/ac97.c | 58 ++++ src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/ck804/ck804_ac97.c | 58 ---- src/southbridge/nvidia/ck804/ck804_early_setup.c | 338 ------------------- .../nvidia/ck804/ck804_early_setup_car.c | 365 --------------------- .../nvidia/ck804/ck804_early_setup_ss.h | 220 ------------- src/southbridge/nvidia/ck804/ck804_early_smbus.c | 80 ----- src/southbridge/nvidia/ck804/ck804_early_smbus.h | 5 - src/southbridge/nvidia/ck804/ck804_enable_rom.c | 40 --- .../nvidia/ck804/ck804_enable_usbdebug.c | 61 ---- src/southbridge/nvidia/ck804/ck804_fadt.c | 147 --------- src/southbridge/nvidia/ck804/ck804_ht.c | 41 --- src/southbridge/nvidia/ck804/ck804_ide.c | 82 ----- src/southbridge/nvidia/ck804/ck804_lpc.c | 345 ------------------- src/southbridge/nvidia/ck804/ck804_nic.c | 136 -------- src/southbridge/nvidia/ck804/ck804_pci.c | 94 ------ src/southbridge/nvidia/ck804/ck804_pcie.c | 52 --- src/southbridge/nvidia/ck804/ck804_reset.c | 55 ---- src/southbridge/nvidia/ck804/ck804_sata.c | 187 ----------- src/southbridge/nvidia/ck804/ck804_smbus.c | 110 ------- src/southbridge/nvidia/ck804/ck804_smbus.h | 229 ------------- src/southbridge/nvidia/ck804/ck804_usb.c | 61 ---- src/southbridge/nvidia/ck804/ck804_usb2.c | 50 --- src/southbridge/nvidia/ck804/early_setup.c | 338 +++++++++++++++++++ src/southbridge/nvidia/ck804/early_setup_car.c | 365 +++++++++++++++++++++ src/southbridge/nvidia/ck804/early_setup_ss.h | 220 +++++++++++++ src/southbridge/nvidia/ck804/early_smbus.c | 80 +++++ src/southbridge/nvidia/ck804/early_smbus.h | 5 + src/southbridge/nvidia/ck804/enable_rom.c | 40 +++ src/southbridge/nvidia/ck804/enable_usbdebug.c | 61 ++++ src/southbridge/nvidia/ck804/fadt.c | 147 +++++++++ src/southbridge/nvidia/ck804/ht.c | 41 +++ src/southbridge/nvidia/ck804/ide.c | 82 +++++ src/southbridge/nvidia/ck804/lpc.c | 345 +++++++++++++++++++ src/southbridge/nvidia/ck804/nic.c | 136 ++++++++ src/southbridge/nvidia/ck804/pci.c | 94 ++++++ src/southbridge/nvidia/ck804/pcie.c | 52 +++ src/southbridge/nvidia/ck804/reset.c | 55 ++++ src/southbridge/nvidia/ck804/sata.c | 187 +++++++++++ src/southbridge/nvidia/ck804/smbus.c | 110 +++++++ src/southbridge/nvidia/ck804/smbus.h | 229 +++++++++++++ src/southbridge/nvidia/ck804/usb.c | 61 ++++ src/southbridge/nvidia/ck804/usb2.c | 50 +++ 44 files changed, 2772 insertions(+), 2772 deletions(-) create mode 100644 src/southbridge/nvidia/ck804/ac97.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_ac97.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_early_setup.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_early_setup_car.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_early_setup_ss.h delete mode 100644 src/southbridge/nvidia/ck804/ck804_early_smbus.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_early_smbus.h delete mode 100644 src/southbridge/nvidia/ck804/ck804_enable_rom.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_fadt.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_ht.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_ide.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_lpc.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_nic.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_pci.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_pcie.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_reset.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_sata.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_smbus.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_smbus.h delete mode 100644 src/southbridge/nvidia/ck804/ck804_usb.c delete mode 100644 src/southbridge/nvidia/ck804/ck804_usb2.c create mode 100644 src/southbridge/nvidia/ck804/early_setup.c create mode 100644 src/southbridge/nvidia/ck804/early_setup_car.c create mode 100644 src/southbridge/nvidia/ck804/early_setup_ss.h create mode 100644 src/southbridge/nvidia/ck804/early_smbus.c create mode 100644 src/southbridge/nvidia/ck804/early_smbus.h create mode 100644 src/southbridge/nvidia/ck804/enable_rom.c create mode 100644 src/southbridge/nvidia/ck804/enable_usbdebug.c create mode 100644 src/southbridge/nvidia/ck804/fadt.c create mode 100644 src/southbridge/nvidia/ck804/ht.c create mode 100644 src/southbridge/nvidia/ck804/ide.c create mode 100644 src/southbridge/nvidia/ck804/lpc.c create mode 100644 src/southbridge/nvidia/ck804/nic.c create mode 100644 src/southbridge/nvidia/ck804/pci.c create mode 100644 src/southbridge/nvidia/ck804/pcie.c create mode 100644 src/southbridge/nvidia/ck804/reset.c create mode 100644 src/southbridge/nvidia/ck804/sata.c create mode 100644 src/southbridge/nvidia/ck804/smbus.c create mode 100644 src/southbridge/nvidia/ck804/smbus.h create mode 100644 src/southbridge/nvidia/ck804/usb.c create mode 100644 src/southbridge/nvidia/ck804/usb2.c (limited to 'src/southbridge/nvidia/ck804') diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 09b20708af..b1577f553a 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -1,22 +1,22 @@ driver-y += ck804.c -driver-y += ck804_usb.c -driver-y += ck804_lpc.c -driver-y += ck804_smbus.c -driver-y += ck804_ide.c -driver-y += ck804_sata.c -driver-y += ck804_usb2.c -driver-y += ck804_ac97.c -driver-y += ck804_nic.c -driver-y += ck804_pci.c -driver-y += ck804_pcie.c -driver-y += ck804_ht.c +driver-y += usb.c +driver-y += lpc.c +driver-y += smbus.c +driver-y += ide.c +driver-y += sata.c +driver-y += usb2.c +driver-y += ac97.c +driver-y += nic.c +driver-y += pci.c +driver-y += pcie.c +driver-y += ht.c -ramstage-y += ck804_reset.c +ramstage-y += reset.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c -romstage-y += ck804_enable_usbdebug.c -romstage-y += ck804_early_smbus.c +romstage-y += enable_usbdebug.c +romstage-y += early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds diff --git a/src/southbridge/nvidia/ck804/ac97.c b/src/southbridge/nvidia/ck804/ac97.c new file mode 100644 index 0000000000..20b3cfb4b2 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ac97.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static struct device_operations ac97audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + // .enable = ck804_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver ac97audio_driver __pci_driver = { + .ops = &ac97audio_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, +}; + +static struct device_operations ac97modem_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + // .enable = ck804_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver ac97modem_driver __pci_driver = { + .ops = &ac97modem_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_MCI, +}; diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 5c829e121d..6d4b6a4777 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -20,7 +20,7 @@ #include #include -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" +#include "southbridge/nvidia/ck804/enable_rom.c" static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/nvidia/ck804/ck804_ac97.c b/src/southbridge/nvidia/ck804/ck804_ac97.c deleted file mode 100644 index 20b3cfb4b2..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_ac97.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -static struct device_operations ac97audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - // .enable = ck804_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, -}; - -static struct device_operations ac97modem_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - // .enable = ck804_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_MCI, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c deleted file mode 100644 index 53d35feecc..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_early_setup.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include - -static int set_ht_link_ck804(uint8_t ht_c_num) -{ - unsigned vendorid = 0x10de; - unsigned val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned index, unsigned where, unsigned control, - const unsigned int *register_values, int max) -{ - int i; - unsigned val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); - - for (i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); -} - -#define ANACTRL_IO_BASE 0x7000 -#define ANACTRL_REG_POS 0x68 - -#define SYSCTRL_IO_BASE 0x6000 -#define SYSCTRL_REG_POS 0x64 - -/* - * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. - * Apparently some sort of lane configuration. - * - * 16 1 1 2 :0 - * 8 8 2 2 :1 - * 8 8 4 :2 - * 8 4 4 4 :3 - * 16 4 :4 - */ - -#if CONFIG_CK804_NUM > 1 -#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) -#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000) -#ifndef CK804B_BUSN -#define CK804B_BUSN 0x80 -#endif -#endif - -#define CK804_CHIP_REV 3 - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 -#define CK804B_DEVN_BASE 1 -#else -#define CK804B_DEVN_BASE CK804_DEVN_BASE -#endif - -static void ck804_early_set_port(void) -{ - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, -#endif - - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, -#endif - }; - - setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); -} - -static void ck804_early_clear_port(void) -{ - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, -#endif - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, -#if CONFIG_CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, -#endif - }; - - setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); -} - -static void ck804_early_setup(void) -{ - static const unsigned int ctrl_conf[] = { - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, -#endif - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, - -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), - -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, -#endif - - /* Activate master port on primary SATA controller. */ - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, -#if CONFIG_CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, -#endif - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), -#endif - - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CONFIG_CK804_USE_NIC - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - -#if CONFIG_CK804_USE_ACI - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), -#endif - -#if CONFIG_CK804_NUM > 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), -#endif - -#if CONFIG_CK804_NUM > 1 -#if CONFIG_CK804_USE_NIC - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif -#endif - -#ifdef CK804_MB_SETUP - CK804_MB_SETUP -#endif - }; - - setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); - - setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - -#if CONFIG_CK804_NUM > 1 - setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); -#endif - -#if 0 - dump_io_resources(ANACTRL_IO_BASE); - dump_io_resources(SYSCTRL_IO_BASE); -#endif -} - -static int ck804_early_setup_x(void) -{ - ck804_early_set_port(); - ck804_early_setup(); - ck804_early_clear_port(); - return set_ht_link_ck804(4); -} - -void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void soft_reset(void) -{ - set_bios_reset(); - - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -} diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c deleted file mode 100644 index 23a83ff400..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static int set_ht_link_ck804(uint8_t ht_c_num) -{ - unsigned vendorid = 0x10de; - unsigned val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned index, unsigned where, unsigned control, - const unsigned int *register_values, int max) -{ - int i; - unsigned val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); - - for (i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); -} - -#define ANACTRL_IO_BASE 0x3000 -#define ANACTRL_REG_POS 0x68 - -#define SYSCTRL_IO_BASE 0x2000 -#define SYSCTRL_REG_POS 0x64 - -/* - * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. - * Apparently some sort of lane configuration. - * - * 16 1 1 2 :0 - * 8 8 2 2 :1 - * 8 8 4 :2 - * 8 4 4 4 :3 - * 16 4 :4 - */ - -#define CK804_CHIP_REV 3 - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 -#define CK804B_DEVN_BASE 1 -#else -#define CK804B_DEVN_BASE CK804_DEVN_BASE -#endif - -static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, - unsigned *io_base) -{ - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - }; - - int j; - for (j = 0; j < ck804_num; j++) { - u32 dev; - if (busn[j] == 0) //sb chain - dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); - setup_resource_map_offset(ctrl_devport_conf, - ARRAY_SIZE(ctrl_devport_conf), dev, - io_base[j]); - } -} - -static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, - unsigned *io_base) -{ - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, - PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, - }; - - int j; - for (j = 0; j < ck804_num; j++) { - u32 dev; - if (busn[j] == 0) //sb chain - dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); - setup_resource_map_offset(ctrl_devport_conf_clear, - ARRAY_SIZE(ctrl_devport_conf_clear), dev, - io_base[j]); - } -} - -static void ck804_early_setup(unsigned ck804_num, unsigned *busn, - unsigned *io_base) -{ - static const unsigned int ctrl_conf_master[] = { - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xac), 0xffffff00, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, - - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, - -#ifdef CK804_MB_SETUP - CK804_MB_SETUP -#endif - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - - /* Activate master port on primary SATA controller. */ - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), - -//SYSCTRL - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CONFIG_CK804_USE_NIC - RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - -#if CONFIG_CK804_USE_ACI - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), -#endif - - }; - - static const unsigned int ctrl_conf_multiple[] = { - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), - }; - - static const unsigned int ctrl_conf_slave[] = { - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, - - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - -/* This line doesn't exist in the non-CAR version. */ - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), - -#if CONFIG_CK804_USE_NIC - RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - }; - - int j; - for (j = 0; j < ck804_num; j++) { - if (busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, - ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]); - if (ck804_num > 1) - setup_resource_map_x_offset(ctrl_conf_multiple, - ARRAY_SIZE(ctrl_conf_multiple), - PCI_DEV(0, CK804_DEVN_BASE, 0), 0); - - continue; - } - - setup_resource_map_x_offset(ctrl_conf_slave, - ARRAY_SIZE(ctrl_conf_slave), - PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); - } - - for (j = 0; j < ck804_num; j++) { - /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ - /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ - /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, - pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, - sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, - cpu_ss_tbl, 64); - } -} - -static int ck804_early_setup_x(void) -{ - unsigned busn[4], io_base[4]; - int i, ck804_num = 0; - - for (i = 0; i < 4; i++) { - uint32_t id; - device_t dev; - if (i == 0) // SB chain - dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (id == 0x005e10de) { - busn[ck804_num] = i * 0x40; - io_base[ck804_num] = i * 0x4000; - ck804_num++; - } - } - - ck804_early_set_port(ck804_num, busn, io_base); - ck804_early_setup(ck804_num, busn, io_base); - ck804_early_clear_port(ck804_num, busn, io_base); - - return set_ht_link_ck804(4); -} - -void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void soft_reset(void) -{ - set_bios_reset(); - - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -} diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h b/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h deleted file mode 100644 index 39ae8c1a17..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static const unsigned int pcie_ss_tbl[] = { - 0x0C504103f, - 0x0C504103f, - 0x0C504103f, - 0x0C5042040, - 0x0C5042040, - 0x0C5042040, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5049047, - 0x0C5049047, - 0x0C5049047, - 0x0C504a048, - 0x0C504a048, - 0x0C504b049, - 0x0C504b049, - 0x0C504a048, - 0x0C504a048, - 0x0C5049047, - 0x0C5049047, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5043041, - 0x0C5043041, - 0x0C5042040, - 0x0C5042040, -}; - -static const unsigned int sata_ss_tbl[] = { - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, -}; - -static const unsigned int cpu_ss_tbl[] = { - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c deleted file mode 100644 index 05dcd98014..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "ck804_smbus.h" -#include "ck804_early_smbus.h" - -#define SMBUS_BAR_BASE 0x20 -#define SMBUS_IO_BASE 0x1000 -#define SMBUS_IO_SIZE 0x0040 - -#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x)) -#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x)) - -void enable_smbus(void) -{ - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); - if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\n"); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1); - pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, 0x4, 0x01); - - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); - outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT); - - print_debug("SMBus controller enabled\n"); -} - -int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_BASE(bus), device, address); -} - -int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, - unsigned char val) -{ - return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - return ck804_smbus_read_byte(0, device, address); -} - -int smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return ck804_smbus_write_byte(0, device, address, val); -} diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.h b/src/southbridge/nvidia/ck804/ck804_early_smbus.h deleted file mode 100644 index cf25403fdd..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_early_smbus.h +++ /dev/null @@ -1,5 +0,0 @@ -int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); -int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); -void enable_smbus(void); -int smbus_read_byte(unsigned int, unsigned int); -int smbus_write_byte(unsigned int, unsigned int, unsigned char); diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c deleted file mode 100644 index facf7959eb..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -static void ck804_enable_rom(void) -{ - unsigned char byte; - device_t addr; - - /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ - /* Locate the ck804 LPC. */ - addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); - - /* Set the 4MB enable bit. */ - byte = pci_read_config8(addr, 0x88); - byte |= 0x80; - pci_write_config8(addr, 0x88, byte); -} diff --git a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c deleted file mode 100644 index 3cccded343..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -void set_debug_port(unsigned int port) -{ - u32 dword; - device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ - - /* Write the port number to 0x74[15:12]. */ - dword = pci_read_config32(dev, 0x74); - dword &= ~(0xf << 12); - dword |= (port << 12); - pci_write_config32(dev, 0x74, dword); -} - -void ck804_enable_usbdebug(unsigned int port) -{ - device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ - - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); -} diff --git a/src/southbridge/nvidia/ck804/ck804_fadt.c b/src/southbridge/nvidia/ck804/ck804_fadt.c deleted file mode 100644 index a315a32b96..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_fadt.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - * (C) Copyright 2005 Stefan Reinauer - */ - -#include -#include -#include - -extern unsigned pm_base; /* pm_base should be set in sb acpi */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); -#ifdef LONG_FADT - header->length = 244; - header->revision = 3; -#else - header->length = 0x74; - header->revision = 1; -#endif - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "CB-FADT ", 8); - memcpy(header->asl_compiler_id, "IASL", 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile = 0; - fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = pm_base + 0x04; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = pm_base + 0x1c; - fadt->pm_tmr_blk = pm_base + 0x08; - fadt->gpe0_blk = pm_base + 0x20; - fadt->gpe1_blk = 0x0000; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 0xffff; - fadt->p_lvl3_lat = 0xffff; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - fadt->iapc_boot_arch = 0; - fadt->flags = 0xa5; - -#ifdef LONG_FADT - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pm_base; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pm_base + 4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pm_base + 0x08; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pm_base + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 64; - fadt->x_gpe1_blk.bit_offset = 16; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = pm_base + 0xb0; - fadt->x_gpe1_blk.addrh = 0x0; -#endif - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/southbridge/nvidia/ck804/ck804_ht.c b/src/southbridge/nvidia/ck804/ck804_ht.c deleted file mode 100644 index 7a63d97b56..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_ht.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_ide.c b/src/southbridge/nvidia/ck804/ck804_ide.c deleted file mode 100644 index 47f451e6eb..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_ide.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_nvidia_ck804_config *conf; - uint32_t dword; - uint16_t word; - uint8_t byte; - - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled. */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary IDE interface. */ - word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1 \t"); - } - if (conf->ide0_enable) { - /* Enable primary IDE interface. */ - word |= (1 << 1); - printk(BIOS_DEBUG, "IDE0\n"); - } - - word |= (1 << 12); - word |= (1 << 14); - - pci_write_config16(dev, 0x50, word); - - byte = 0x20; /* Latency: 64 --> 32 */ - pci_write_config8(dev, 0xd, byte); - - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); - -#if CONFIG_PCI_ROM_RUN == 1 - pci_dev_init(dev); -#endif -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c deleted file mode 100644 index b3f14bfe18..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2003 SuSE Linux AG - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ck804.h" - -#define CK804_CHIP_REV 2 - -#define NMI_OFF 0 - -// 0x7a or e3 -#define PREVIOUS_POWER_STATE 0x7A - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -static void lpc_common_init(device_t dev) -{ - uint8_t byte; - uint32_t dword; - - /* I/O APIC initialization */ - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 0); /* Enable APIC. */ - pci_write_config8(dev, 0x74, byte); - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ - - setup_ioapic(dword, 0); // Don't rename IOAPIC ID - -#if 1 - dword = pci_read_config32(dev, 0xe4); - dword |= (1 << 23); - pci_write_config32(dev, 0xe4, dword); -#endif -} - -static void lpc_slave_init(device_t dev) -{ - lpc_common_init(dev); -} - -static void rom_dummy_write(device_t dev) -{ - uint8_t old, new; - uint8_t *p; - - old = pci_read_config8(dev, 0x88); - new = old | 0xc0; - if (new != old) - pci_write_config8(dev, 0x88, new); - /* Enable write. */ - old = pci_read_config8(dev, 0x6d); - new = old | 0x01; - if (new != old) - pci_write_config8(dev, 0x6d, new); - - /* Dummy write. */ - p = (uint8_t *) 0xffffffe0; - old = 0; - *p = old; - old = *p; - - /* Disable write. */ - old = pci_read_config8(dev, 0x6d); - new = old & 0xfe; - if (new != old) - pci_write_config8(dev, 0x6d, new); -} - -static void enable_hpet(struct device *dev) -{ - unsigned long hpet_address; - - pci_write_config32(dev, 0x44, 0xfed00001); - hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; - printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); -} - -unsigned pm_base=0; - -static void lpc_init(device_t dev) -{ - uint8_t byte, byte_old; - int on, nmi_option; - - lpc_common_init(dev); - - pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); - -#if CK804_CHIP_REV==1 - if (dev->bus->secondary != 1) - return; -#endif - -#if 0 - /* Posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif - - /* power after power fail */ - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; - if (!on) - byte |= 0x40; - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); - - /* Throttle the CPU speed down for testing. */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if (on) { - uint16_t pm10_bar; - uint32_t dword; - pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); - outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); - on = 8 - on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); - } -#if 0 -// default is enabled - /* Enable Port 92 fast reset. */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - - /* Enable Error reporting. */ - /* Set up sync flood detected. */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors. */ - byte = inb(0x70); /* RTC70 */ - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* Set NMI. */ - } else { - byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ - } - if (byte != byte_old) - outb(byte, 0x70); - - /* Initialize the real time clock (RTC). */ - rtc_init(0); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers (HPET). */ - enable_hpet(dev); - - rom_dummy_write(dev); -} - -static void ck804_lpc_read_resources(device_t dev) -{ - struct resource *res; - unsigned long index; - - /* Get the normal PCI resources of this device. */ - /* We got one for APIC, or one more for TRAP. */ - pci_dev_read_resources(dev); - - /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ - for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ - pci_get_resource(dev, index); - compact_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -/** - * Enable resources for children devices. - * - * This function is called by the global enable_resources() indirectly via the - * device_operation::enable_resources() method of devices. - * - */ -static void ck804_lpc_enable_childrens_resources(device_t dev) -{ - struct bus *link; - uint32_t reg, reg_var[4]; - int i, var_num = 0; - - reg = pci_read_config32(dev, 0xa0); - - for (link = dev->link_list; link; link = link->next) { - device_t child; - for (child = link->children; child; child = child->sibling) { - if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); - switch (base) { - case 0x3f8: // COM1 - reg |= (1 << 0); - break; - case 0x2f8: // COM2 - reg |= (1 << 1); - break; - case 0x378: // Parallel 1 - reg |= (1 << 24); - break; - case 0x3f0: // FD0 - reg |= (1 << 20); - break; - case 0x220: // Audio 0 - reg |= (1 << 8); - break; - case 0x300: // Midi 0 - reg |= (1 << 12); - break; - } - if (base == 0x290 || base >= 0x400) { - if (var_num >= 4) - continue; // only 4 var ; compact them ? - reg |= (1 << (28 + var_num)); - reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); - } - } - } - } - } - pci_write_config32(dev, 0xa0, reg); - for (i = 0; i < var_num; i++) - pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); -} - -static void ck804_lpc_enable_resources(device_t dev) -{ - pci_dev_enable_resources(dev); - ck804_lpc_enable_childrens_resources(dev); -} - -static struct device_operations lpc_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = ck804_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC, -}; - -static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, -}; - -#if CK804_CHIP_REV == 1 -static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, -}; -#else -static struct device_operations lpc_slave_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_slave_init, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, -}; -#endif diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/ck804_nic.c deleted file mode 100644 index 8e1bddf9e2..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_nic.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "ck804.h" - -static void nic_init(struct device *dev) -{ - uint32_t dword, old, mac_h, mac_l; - int eeprom_valid = 0; - struct southbridge_nvidia_ck804_config *conf; - static uint32_t nic_index = 0; - unsigned long base; - struct resource *res; - - res = find_resource(dev, 0x10); - base = (unsigned long)res->base; - -#define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 - - write32(base + NvRegPhyInterface, PHY_RGMII); - - old = dword = pci_read_config32(dev, 0x30); - dword &= ~(0xf); - dword |= 0xf; - if (old != dword) - pci_write_config32(dev, 0x30, dword); - - conf = dev->chip_info; - - if (conf->mac_eeprom_smbus != 0) { - /* Read MAC address from EEPROM at first. */ - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, - conf->mac_eeprom_addr); - - if (dev_eeprom) { - /* If that is valid we will use that. */ - unsigned char dat[6]; - int i, status; - for (i = 0; i < 6; i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) - break; - dat[i] = status & 0xff; - } - if (status >= 0) { - mac_l = 0; - for (i = 3; i >= 0; i--) { - mac_l <<= 8; - mac_l += dat[i]; - } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i = 5; i >= 4; i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } - } - } - } - - /* If that is invalid we will read that from romstrap. */ - if (!eeprom_valid) { - unsigned long mac_pos; - mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ - mac_l = read32(mac_pos) + nic_index; - mac_h = read32(mac_pos + 4); - } -#if 1 - /* Set that into NIC MMIO. */ -#define NvRegMacAddrA 0xA8 -#define NvRegMacAddrB 0xAC - write32(base + NvRegMacAddrA, mac_l); - write32(base + NvRegMacAddrB, mac_h); -#else - /* Set that into NIC. */ - pci_write_config32(dev, 0xa8, mac_l); - pci_write_config32(dev, 0xac, mac_h); -#endif - - nic_index++; - -#if CONFIG_PCI_ROM_RUN == 1 - pci_dev_init(dev); /* It will init Option ROM. */ -#endif -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, -}; - -static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c deleted file mode 100644 index 044c7100d4..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_pci.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include "ck804.h" - -static void pci_init(struct device *dev) -{ - uint32_t dword; - device_t pci_domain_dev; - struct resource *mem, *pref; - - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - -#if 0 - word = pci_read_config16(dev, 0x48); - word |= (1 << 0); /* MRL2MRM */ - word |= (1 << 2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); -#endif - -#if 1 - dword = pci_read_config32(dev, 0x4c); - dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ - pci_write_config32(dev, 0x4c, dword); -#endif - - pci_domain_dev = dev->bus->dev; - while (pci_domain_dev) { - if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) - break; - pci_domain_dev = pci_domain_dev->bus->dev; - } - - if (!pci_domain_dev) - return; /* Impossible */ - - pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); - mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); - - if (!mem) - return; /* Impossible */ - - if (!pref || pref->base > mem->base) { - dword = mem->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); - } else { - dword = pref->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); - } - - printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); /* TOM */ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - // .enable = ck804_enable, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_pcie.c b/src/southbridge/nvidia/ck804/ck804_pcie.c deleted file mode 100644 index cbde9cf57c..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_pcie.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -static void pcie_init(struct device *dev) -{ - uint32_t dword; - - /* Enable PCI error detecting. */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - // .enable = ck804_enable, -}; - -static const struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_reset.c b/src/southbridge/nvidia/ck804/ck804_reset.c deleted file mode 100644 index 7f73e68d35..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_reset.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9. */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c deleted file mode 100644 index b3ec80422d..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_sata.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include "ck804.h" - -#ifndef CK804_SATA_RESET_FOR_ATAPI -#define CK804_SATA_RESET_FOR_ATAPI 0 -#endif - -#if CK804_SATA_RESET_FOR_ATAPI -static void sata_com_reset(struct device *dev, unsigned reset) -// reset = 1 : reset -// reset = 0 : clear -{ - uint32_t *base; - uint32_t dword; - int loop; - - base = (uint32_t *) pci_read_config32(dev, 0x24); - - printk(BIOS_DEBUG, "base = %08lx\n", base); - - if (reset) { - *(base + 4) = 0xffffffff; - *(base + 0x44) = 0xffffffff; - } - - dword = *(base + 8); - dword &= ~(0xf); - dword |= reset; - - *(base + 8) = dword; - *(base + 0x48) = dword; - -#if 0 - udelay(1000); - dword &= ~(0xf); - *(base + 8) = dword; - *(base + 0x48) = dword; -#endif - - if (reset) - return; - - dword = *(base + 0); - printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); - if (dword == 0x113) { - loop = 200000; // 2 - do { - dword = *(base + 4); - if ((dword & 0x10000) != 0) - break; - udelay(10); - } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); - } - - dword = *(base + 0x40); - printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); - if (dword == 0x113) { - loop = 200000; //2 - do { - dword = *(base + 0x44); - if ((dword & 0x10000) != 0) - break; - udelay(10); - } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); - } -} -#endif - -static void sata_init(struct device *dev) -{ - uint32_t dword; - struct southbridge_nvidia_ck804_config *conf; - - conf = dev->chip_info; - - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled. */ - dword &= ~((1 << 15) | (1 << 13)); - if (conf->sata1_enable) { - /* Enable secondary SATA interface. */ - dword |= (1 << 0); - printk(BIOS_DEBUG, "SATA S \t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface. */ - dword |= (1 << 1); - printk(BIOS_DEBUG, "SATA P \n"); - } -#if 0 - /* Write back */ - dword |= (1 << 12); - dword |= (1 << 14); -#endif - -#if 0 - /* ADMA */ - dword |= (1 << 16); - dword |= (1 << 17); -#endif - -#if 1 - /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ - dword &= ~(0x1f << 24); - dword |= (0x15 << 24); -#endif - pci_write_config32(dev, 0x50, dword); - -#if 0 - /* SLUMBER_DURING_D3 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(1 << 4); - pci_write_config32(dev, 0x7c, dword); - - dword = pci_read_config32(dev, 0xd0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xd0, dword); - - dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xe0, dword); -#endif - - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); - -#if CK804_SATA_RESET_FOR_ATAPI - dword = pci_read_config32(dev, 0xac); - dword &= ~((1 << 13) | (1 << 14)); - dword |= (1 << 13) | (0 << 14); - pci_write_config32(dev, 0xac, dword); - - sata_com_reset(dev, 1); /* For discover some s-atapi device. */ -#endif - -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - // .enable = ck804_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0, -}; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.c b/src/southbridge/nvidia/ck804/ck804_smbus.c deleted file mode 100644 index ca5305065f..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_smbus.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "ck804.h" -#include "ck804_smbus.h" - -static int lsmbus_recv_byte(device_t dev) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(device_t dev, uint8_t val) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(device_t dev, uint8_t address) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) -{ - unsigned device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.h b/src/southbridge/nvidia/ck804/ck804_smbus.h deleted file mode 100644 index 2cdcadce80..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_smbus.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include - -#define SMBHSTSTAT 0x1 -#define SMBHSTPRTCL 0x0 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x2 -#define SMBHSTDAT0 0x4 -#define SMBHSTDAT1 0x5 - -/* - * Between 1-10 seconds, We should never timeout normally. - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -#if 0 -/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) - return 0; - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; -} -#endif - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - if ((val & 0xff) != 0) - return 0; - } while (--loops); - return -3; -} - -#ifndef __PRE_RAM__ -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned char global_status_register, byte; - -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* Set the command/address. */ - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - /* Read results of transaction. */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - /* Lose check, otherwise it should be 0. */ - if (global_status_register != 0x80) - return -1; - - return byte; -} - -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, - unsigned char val) -{ - unsigned global_status_register; - -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Set up for a byte data write. */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - if (global_status_register != 0x80) - return -1; - - return 0; -} -#endif - -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, - unsigned address) -{ - unsigned char global_status_register, byte; - -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* Set the command/address. */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Byte data read */ - outb(0x07, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - /* Read results of transaction. */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - /* Lose check, otherwise it should be 0. */ - if (global_status_register != 0x80) - return -1; - - return byte; -} - -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, - unsigned address, unsigned char val) -{ - unsigned global_status_register; - -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Set up for a byte data write. */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - if (global_status_register != 0x80) - return -1; - - return 0; -} diff --git a/src/southbridge/nvidia/ck804/ck804_usb.c b/src/southbridge/nvidia/ck804/ck804_usb.c deleted file mode 100644 index 45ee734eb1..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_usb.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -static void usb1_init(struct device *dev) -{ - struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; - if (conf->usb1_hc_reset) { - /* - * Somehow the warm reset does not really reset the USB - * controller. Later, during boot, when the Bus Master bit is - * set, the USB controller trashes the memory, causing weird - * misbehavior. Was detected on Sun Ultra40, where mptable - * was damaged. - */ - uint32_t bar0 = pci_read_config32(dev, 0x10); - uint32_t *regs = (uint32_t *) (bar0 & ~0xfff); - - /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ - regs[2] |= 1; - } -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb1_init, - // .enable = ck804_enable, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, -}; diff --git a/src/southbridge/nvidia/ck804/ck804_usb2.c b/src/southbridge/nvidia/ck804/ck804_usb2.c deleted file mode 100644 index e53f38f019..0000000000 --- a/src/southbridge/nvidia/ck804/ck804_usb2.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "ck804.h" - -static void usb2_init(struct device *dev) -{ - uint32_t dword; - dword = pci_read_config32(dev, 0xf8); - dword |= 40; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations usb2_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb2_init, - // .enable = ck804_enable, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_USB2, -}; diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c new file mode 100644 index 0000000000..53d35feecc --- /dev/null +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -0,0 +1,338 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +static int set_ht_link_ck804(uint8_t ht_c_num) +{ + unsigned vendorid = 0x10de; + unsigned val = 0x01610169; + return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); +} + +static void setup_ss_table(unsigned index, unsigned where, unsigned control, + const unsigned int *register_values, int max) +{ + int i; + unsigned val; + + val = inl(control); + val &= 0xfffffffe; + outl(val, control); + + outl(0, index); + + for (i = 0; i < max; i++) { + unsigned long reg; + reg = register_values[i]; + outl(reg, where); + } + val = inl(control); + val |= 1; + outl(val, control); +} + +#define ANACTRL_IO_BASE 0x7000 +#define ANACTRL_REG_POS 0x68 + +#define SYSCTRL_IO_BASE 0x6000 +#define SYSCTRL_REG_POS 0x64 + +/* + * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. + * Apparently some sort of lane configuration. + * + * 16 1 1 2 :0 + * 8 8 2 2 :1 + * 8 8 4 :2 + * 8 4 4 4 :3 + * 16 4 :4 + */ + +#if CONFIG_CK804_NUM > 1 +#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) +#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000) +#ifndef CK804B_BUSN +#define CK804B_BUSN 0x80 +#endif +#endif + +#define CK804_CHIP_REV 3 + +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 +#define CK804B_DEVN_BASE 1 +#else +#define CK804B_DEVN_BASE CK804_DEVN_BASE +#endif + +static void ck804_early_set_port(void) +{ + static const unsigned int ctrl_devport_conf[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, +#if CONFIG_CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, +#endif + + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, +#if CONFIG_CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, +#endif + }; + + setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); +} + +static void ck804_early_clear_port(void) +{ + static const unsigned int ctrl_devport_conf_clear[] = { + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, +#if CONFIG_CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, +#endif + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, +#if CONFIG_CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, +#endif + }; + + setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); +} + +static void ck804_early_setup(void) +{ + static const unsigned int ctrl_conf[] = { + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, + +#if CONFIG_CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, +#endif + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, + +#if CONFIG_CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, +#endif + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, + +#if CONFIG_CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, +#endif + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, + +#if CONFIG_CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, +#endif + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, + +#if CONFIG_CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), + +#if CONFIG_CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, +#if CONFIG_CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, +#endif + + /* Activate master port on primary SATA controller. */ + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, +#if CONFIG_CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), +#if CONFIG_CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, +#if CONFIG_CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), +#if CONFIG_CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), +#endif + + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), +#if CONFIG_CK804_USE_NIC + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), +#endif + +#if CONFIG_CK804_USE_ACI + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), +#endif + +#if CONFIG_CK804_NUM > 1 + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), +#endif + +#if CONFIG_CK804_NUM > 1 +#if CONFIG_CK804_USE_NIC + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), +#endif +#endif + +#ifdef CK804_MB_SETUP + CK804_MB_SETUP +#endif + }; + + setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); + + setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); + +#if CONFIG_CK804_NUM > 1 + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); + setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); +#endif + +#if 0 + dump_io_resources(ANACTRL_IO_BASE); + dump_io_resources(SYSCTRL_IO_BASE); +#endif +} + +static int ck804_early_setup_x(void) +{ + ck804_early_set_port(); + ck804_early_setup(); + ck804_early_clear_port(); + return set_ht_link_ck804(4); +} + +void hard_reset(void) +{ + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +void soft_reset(void) +{ + set_bios_reset(); + + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +} diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c new file mode 100644 index 0000000000..23a83ff400 --- /dev/null +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -0,0 +1,365 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static int set_ht_link_ck804(uint8_t ht_c_num) +{ + unsigned vendorid = 0x10de; + unsigned val = 0x01610169; + return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); +} + +static void setup_ss_table(unsigned index, unsigned where, unsigned control, + const unsigned int *register_values, int max) +{ + int i; + unsigned val; + + val = inl(control); + val &= 0xfffffffe; + outl(val, control); + + outl(0, index); + + for (i = 0; i < max; i++) { + unsigned long reg; + reg = register_values[i]; + outl(reg, where); + } + val = inl(control); + val |= 1; + outl(val, control); +} + +#define ANACTRL_IO_BASE 0x3000 +#define ANACTRL_REG_POS 0x68 + +#define SYSCTRL_IO_BASE 0x2000 +#define SYSCTRL_REG_POS 0x64 + +/* + * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. + * Apparently some sort of lane configuration. + * + * 16 1 1 2 :0 + * 8 8 2 2 :1 + * 8 8 4 :2 + * 8 4 4 4 :3 + * 16 4 :4 + */ + +#define CK804_CHIP_REV 3 + +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 +#define CK804B_DEVN_BASE 1 +#else +#define CK804B_DEVN_BASE CK804_DEVN_BASE +#endif + +static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, + unsigned *io_base) +{ + static const unsigned int ctrl_devport_conf[] = { + PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + }; + + int j; + for (j = 0; j < ck804_num; j++) { + u32 dev; + if (busn[j] == 0) //sb chain + dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); + else + dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); + setup_resource_map_offset(ctrl_devport_conf, + ARRAY_SIZE(ctrl_devport_conf), dev, + io_base[j]); + } +} + +static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, + unsigned *io_base) +{ + static const unsigned int ctrl_devport_conf_clear[] = { + PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, + PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, + }; + + int j; + for (j = 0; j < ck804_num; j++) { + u32 dev; + if (busn[j] == 0) //sb chain + dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); + else + dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); + setup_resource_map_offset(ctrl_devport_conf_clear, + ARRAY_SIZE(ctrl_devport_conf_clear), dev, + io_base[j]); + } +} + +static void ck804_early_setup(unsigned ck804_num, unsigned *busn, + unsigned *io_base) +{ + static const unsigned int ctrl_conf_master[] = { + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xac), 0xffffff00, 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, + + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + +#ifdef CK804_MB_SETUP + CK804_MB_SETUP +#endif + + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + + /* Activate master port on primary SATA controller. */ + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xe0), ~(0xf0000000), 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), + +//SYSCTRL + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), +#if CONFIG_CK804_USE_NIC + RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), +#endif + +#if CONFIG_CK804_USE_ACI + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), +#endif + + }; + + static const unsigned int ctrl_conf_multiple[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), + }; + + static const unsigned int ctrl_conf_slave[] = { + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, + + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, + +/* This line doesn't exist in the non-CAR version. */ + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), + +#if CONFIG_CK804_USE_NIC + RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), +#endif + }; + + int j; + for (j = 0; j < ck804_num; j++) { + if (busn[j] == 0) { + setup_resource_map_x_offset(ctrl_conf_master, + ARRAY_SIZE(ctrl_conf_master), + PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]); + if (ck804_num > 1) + setup_resource_map_x_offset(ctrl_conf_multiple, + ARRAY_SIZE(ctrl_conf_multiple), + PCI_DEV(0, CK804_DEVN_BASE, 0), 0); + + continue; + } + + setup_resource_map_x_offset(ctrl_conf_slave, + ARRAY_SIZE(ctrl_conf_slave), + PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); + } + + for (j = 0; j < ck804_num; j++) { + /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ + /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ + /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, + io_base[j] + ANACTRL_IO_BASE + 0x44, + io_base[j] + ANACTRL_IO_BASE + 0x48, + pcie_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, + io_base[j] + ANACTRL_IO_BASE + 0xb4, + io_base[j] + ANACTRL_IO_BASE + 0xb8, + sata_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, + io_base[j] + ANACTRL_IO_BASE + 0xc4, + io_base[j] + ANACTRL_IO_BASE + 0xc8, + cpu_ss_tbl, 64); + } +} + +static int ck804_early_setup_x(void) +{ + unsigned busn[4], io_base[4]; + int i, ck804_num = 0; + + for (i = 0; i < 4; i++) { + uint32_t id; + device_t dev; + if (i == 0) // SB chain + dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); + else + dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (id == 0x005e10de) { + busn[ck804_num] = i * 0x40; + io_base[ck804_num] = i * 0x4000; + ck804_num++; + } + } + + ck804_early_set_port(ck804_num, busn, io_base); + ck804_early_setup(ck804_num, busn, io_base); + ck804_early_clear_port(ck804_num, busn, io_base); + + return set_ht_link_ck804(4); +} + +void hard_reset(void) +{ + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +void soft_reset(void) +{ + set_bios_reset(); + + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +} diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h new file mode 100644 index 0000000000..39ae8c1a17 --- /dev/null +++ b/src/southbridge/nvidia/ck804/early_setup_ss.h @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const unsigned int pcie_ss_tbl[] = { + 0x0C504103f, + 0x0C504103f, + 0x0C504103f, + 0x0C5042040, + 0x0C5042040, + 0x0C5042040, + 0x0C5043041, + 0x0C5043041, + 0x0C5043041, + 0x0C5043041, + 0x0C5044042, + 0x0C5044042, + 0x0C5044042, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5048046, + 0x0C5048046, + 0x0C5048046, + 0x0C5048046, + 0x0C5049047, + 0x0C5049047, + 0x0C5049047, + 0x0C504a048, + 0x0C504a048, + 0x0C504b049, + 0x0C504b049, + 0x0C504a048, + 0x0C504a048, + 0x0C5049047, + 0x0C5049047, + 0x0C5048046, + 0x0C5048046, + 0x0C5048046, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5044042, + 0x0C5044042, + 0x0C5044042, + 0x0C5043041, + 0x0C5043041, + 0x0C5042040, + 0x0C5042040, +}; + +static const unsigned int sata_ss_tbl[] = { + 0x0c9044042, + 0x0c9044042, + 0x0c9044042, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9044042, + 0x0c9044042, + 0x0c9044042, +}; + +static const unsigned int cpu_ss_tbl[] = { + 0x0C5038036, + 0x0C5038036, + 0x0C5038036, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5038036, + 0x0C5038036, + 0x0C5038036, + 0x0C5038036, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503b039, + 0x0C503b039, + 0x0C503b039, + 0x0C503b039, + 0x0C503b039, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, +}; diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c new file mode 100644 index 0000000000..70f8744c25 --- /dev/null +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "smbus.h" +#include "early_smbus.h" + +#define SMBUS_BAR_BASE 0x20 +#define SMBUS_IO_BASE 0x1000 +#define SMBUS_IO_SIZE 0x0040 + +#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x)) +#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x)) + +void enable_smbus(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); + if (dev == PCI_DEV_INVALID) + die("SMBus controller not found\n"); + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1); + pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, 0x4, 0x01); + + /* Clear any lingering errors, so the transaction will run. */ + outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); + outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT); + + print_debug("SMBus controller enabled\n"); +} + +int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_BASE(bus), device, address); +} + +int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, + unsigned char val) +{ + return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); +} + +int smbus_read_byte(unsigned device, unsigned address) +{ + return ck804_smbus_read_byte(0, device, address); +} + +int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + return ck804_smbus_write_byte(0, device, address, val); +} diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h new file mode 100644 index 0000000000..cf25403fdd --- /dev/null +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -0,0 +1,5 @@ +int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); +int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); +void enable_smbus(void); +int smbus_read_byte(unsigned int, unsigned int); +int smbus_write_byte(unsigned int, unsigned int, unsigned char); diff --git a/src/southbridge/nvidia/ck804/enable_rom.c b/src/southbridge/nvidia/ck804/enable_rom.c new file mode 100644 index 0000000000..facf7959eb --- /dev/null +++ b/src/southbridge/nvidia/ck804/enable_rom.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +static void ck804_enable_rom(void) +{ + unsigned char byte; + device_t addr; + + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ + /* Locate the ck804 LPC. */ + addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); + + /* Set the 4MB enable bit. */ + byte = pci_read_config8(addr, 0x88); + byte |= 0x80; + pci_write_config8(addr, 0x88, byte); +} diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c new file mode 100644 index 0000000000..3cccded343 --- /dev/null +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +void set_debug_port(unsigned int port) +{ + u32 dword; + device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ + + /* Write the port number to 0x74[15:12]. */ + dword = pci_read_config32(dev, 0x74); + dword &= ~(0xf << 12); + dword |= (port << 12); + pci_write_config32(dev, 0x74, dword); +} + +void ck804_enable_usbdebug(unsigned int port) +{ + device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ + + /* Mark the requested physical USB port (1-15) as the Debug Port. */ + set_debug_port(port); + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); +} diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c new file mode 100644 index 0000000000..a315a32b96 --- /dev/null +++ b/src/southbridge/nvidia/ck804/fadt.c @@ -0,0 +1,147 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer + */ + +#include +#include +#include + +extern unsigned pm_base; /* pm_base should be set in sb acpi */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); +#ifdef LONG_FADT + header->length = 244; + header->revision = 3; +#else + header->length = 0x74; + header->revision = 1; +#endif + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "CB-FADT ", 8); + memcpy(header->asl_compiler_id, "IASL", 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + // disable system management mode by setting to 0: + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = pm_base; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = pm_base + 0x04; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = pm_base + 0x1c; + fadt->pm_tmr_blk = pm_base + 0x08; + fadt->gpe0_blk = pm_base + 0x20; + fadt->gpe1_blk = 0x0000; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 0xffff; + fadt->p_lvl3_lat = 0xffff; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0; + fadt->flags = 0xa5; + +#ifdef LONG_FADT + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pm_base; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pm_base + 4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pm_base + 0x08; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pm_base + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = pm_base + 0xb0; + fadt->x_gpe1_blk.addrh = 0x0; +#endif + header->checksum = acpi_checksum((void *)fadt, header->length); +} diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c new file mode 100644 index 0000000000..7a63d97b56 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ht.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static struct device_operations ht_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver ht_driver __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, +}; diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c new file mode 100644 index 0000000000..47f451e6eb --- /dev/null +++ b/src/southbridge/nvidia/ck804/ide.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_nvidia_ck804_config *conf; + uint32_t dword; + uint16_t word; + uint8_t byte; + + conf = dev->chip_info; + + word = pci_read_config16(dev, 0x50); + /* Ensure prefetch is disabled. */ + word &= ~((1 << 15) | (1 << 13)); + if (conf->ide1_enable) { + /* Enable secondary IDE interface. */ + word |= (1 << 0); + printk(BIOS_DEBUG, "IDE1 \t"); + } + if (conf->ide0_enable) { + /* Enable primary IDE interface. */ + word |= (1 << 1); + printk(BIOS_DEBUG, "IDE0\n"); + } + + word |= (1 << 12); + word |= (1 << 14); + + pci_write_config16(dev, 0x50, word); + + byte = 0x20; /* Latency: 64 --> 32 */ + pci_write_config8(dev, 0xd, byte); + + dword = pci_read_config32(dev, 0xf8); + dword |= 12; + pci_write_config32(dev, 0xf8, dword); + +#if CONFIG_PCI_ROM_RUN == 1 + pci_dev_init(dev); +#endif +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, +}; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c new file mode 100644 index 0000000000..b3f14bfe18 --- /dev/null +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -0,0 +1,345 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2003 SuSE Linux AG + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ck804.h" + +#define CK804_CHIP_REV 2 + +#define NMI_OFF 0 + +// 0x7a or e3 +#define PREVIOUS_POWER_STATE 0x7A + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define SLOW_CPU_OFF 0 +#define SLOW_CPU__ON 1 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +static void lpc_common_init(device_t dev) +{ + uint8_t byte; + uint32_t dword; + + /* I/O APIC initialization */ + byte = pci_read_config8(dev, 0x74); + byte |= (1 << 0); /* Enable APIC. */ + pci_write_config8(dev, 0x74, byte); + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ + + setup_ioapic(dword, 0); // Don't rename IOAPIC ID + +#if 1 + dword = pci_read_config32(dev, 0xe4); + dword |= (1 << 23); + pci_write_config32(dev, 0xe4, dword); +#endif +} + +static void lpc_slave_init(device_t dev) +{ + lpc_common_init(dev); +} + +static void rom_dummy_write(device_t dev) +{ + uint8_t old, new; + uint8_t *p; + + old = pci_read_config8(dev, 0x88); + new = old | 0xc0; + if (new != old) + pci_write_config8(dev, 0x88, new); + /* Enable write. */ + old = pci_read_config8(dev, 0x6d); + new = old | 0x01; + if (new != old) + pci_write_config8(dev, 0x6d, new); + + /* Dummy write. */ + p = (uint8_t *) 0xffffffe0; + old = 0; + *p = old; + old = *p; + + /* Disable write. */ + old = pci_read_config8(dev, 0x6d); + new = old & 0xfe; + if (new != old) + pci_write_config8(dev, 0x6d, new); +} + +static void enable_hpet(struct device *dev) +{ + unsigned long hpet_address; + + pci_write_config32(dev, 0x44, 0xfed00001); + hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; + printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); +} + +unsigned pm_base=0; + +static void lpc_init(device_t dev) +{ + uint8_t byte, byte_old; + int on, nmi_option; + + lpc_common_init(dev); + + pm_base = pci_read_config32(dev, 0x60) & 0xff00; + printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); + +#if CK804_CHIP_REV==1 + if (dev->bus->secondary != 1) + return; +#endif + +#if 0 + /* Posted memory write enable */ + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1 << 0)); +#endif + + /* power after power fail */ + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&on, "power_on_after_fail"); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte &= ~0x40; + if (!on) + byte |= 0x40; + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); + + /* Throttle the CPU speed down for testing. */ + on = SLOW_CPU_OFF; + get_option(&on, "slow_cpu"); + if (on) { + uint16_t pm10_bar; + uint32_t dword; + pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); + outl(((on << 1) + 0x10), (pm10_bar + 0x10)); + dword = inl(pm10_bar + 0x10); + on = 8 - on; + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", + (on * 12) + (on >> 1), (on & 1) * 5); + } +#if 0 +// default is enabled + /* Enable Port 92 fast reset. */ + byte = pci_read_config8(dev, 0xe8); + byte |= ~(1 << 3); + pci_write_config8(dev, 0xe8, byte); +#endif + + /* Enable Error reporting. */ + /* Set up sync flood detected. */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors. */ + byte = inb(0x70); /* RTC70 */ + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* Set NMI. */ + } else { + byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ + } + if (byte != byte_old) + outb(byte, 0x70); + + /* Initialize the real time clock (RTC). */ + rtc_init(0); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers (HPET). */ + enable_hpet(dev); + + rom_dummy_write(dev); +} + +static void ck804_lpc_read_resources(device_t dev) +{ + struct resource *res; + unsigned long index; + + /* Get the normal PCI resources of this device. */ + /* We got one for APIC, or one more for TRAP. */ + pci_dev_read_resources(dev); + + /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ + for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ + pci_get_resource(dev, index); + compact_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/** + * Enable resources for children devices. + * + * This function is called by the global enable_resources() indirectly via the + * device_operation::enable_resources() method of devices. + * + */ +static void ck804_lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + uint32_t reg, reg_var[4]; + int i, var_num = 0; + + reg = pci_read_config32(dev, 0xa0); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; child = child->sibling) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + unsigned long base, end; // don't need long long + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); + printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); + switch (base) { + case 0x3f8: // COM1 + reg |= (1 << 0); + break; + case 0x2f8: // COM2 + reg |= (1 << 1); + break; + case 0x378: // Parallel 1 + reg |= (1 << 24); + break; + case 0x3f0: // FD0 + reg |= (1 << 20); + break; + case 0x220: // Audio 0 + reg |= (1 << 8); + break; + case 0x300: // Midi 0 + reg |= (1 << 12); + break; + } + if (base == 0x290 || base >= 0x400) { + if (var_num >= 4) + continue; // only 4 var ; compact them ? + reg |= (1 << (28 + var_num)); + reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); + } + } + } + } + } + pci_write_config32(dev, 0xa0, reg); + for (i = 0; i < var_num; i++) + pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); +} + +static void ck804_lpc_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + ck804_lpc_enable_childrens_resources(dev); +} + +static struct device_operations lpc_ops = { + .read_resources = ck804_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = ck804_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC, +}; + +static const struct pci_driver lpc_driver_pro __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, +}; + +#if CK804_CHIP_REV == 1 +static const struct pci_driver lpc_driver_slave __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, +}; +#else +static struct device_operations lpc_slave_ops = { + .read_resources = ck804_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_slave_init, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver lpc_driver_slave __pci_driver = { + .ops = &lpc_slave_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, +}; +#endif diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c new file mode 100644 index 0000000000..8e1bddf9e2 --- /dev/null +++ b/src/southbridge/nvidia/ck804/nic.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ck804.h" + +static void nic_init(struct device *dev) +{ + uint32_t dword, old, mac_h, mac_l; + int eeprom_valid = 0; + struct southbridge_nvidia_ck804_config *conf; + static uint32_t nic_index = 0; + unsigned long base; + struct resource *res; + + res = find_resource(dev, 0x10); + base = (unsigned long)res->base; + +#define NvRegPhyInterface 0xC0 +#define PHY_RGMII 0x10000000 + + write32(base + NvRegPhyInterface, PHY_RGMII); + + old = dword = pci_read_config32(dev, 0x30); + dword &= ~(0xf); + dword |= 0xf; + if (old != dword) + pci_write_config32(dev, 0x30, dword); + + conf = dev->chip_info; + + if (conf->mac_eeprom_smbus != 0) { + /* Read MAC address from EEPROM at first. */ + struct device *dev_eeprom; + dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, + conf->mac_eeprom_addr); + + if (dev_eeprom) { + /* If that is valid we will use that. */ + unsigned char dat[6]; + int i, status; + for (i = 0; i < 6; i++) { + status = smbus_read_byte(dev_eeprom, i); + if (status < 0) + break; + dat[i] = status & 0xff; + } + if (status >= 0) { + mac_l = 0; + for (i = 3; i >= 0; i--) { + mac_l <<= 8; + mac_l += dat[i]; + } + if (mac_l != 0xffffffff) { + mac_l += nic_index; + mac_h = 0; + for (i = 5; i >= 4; i--) { + mac_h <<= 8; + mac_h += dat[i]; + } + eeprom_valid = 1; + } + } + } + } + + /* If that is invalid we will read that from romstrap. */ + if (!eeprom_valid) { + unsigned long mac_pos; + mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ + mac_l = read32(mac_pos) + nic_index; + mac_h = read32(mac_pos + 4); + } +#if 1 + /* Set that into NIC MMIO. */ +#define NvRegMacAddrA 0xA8 +#define NvRegMacAddrB 0xAC + write32(base + NvRegMacAddrA, mac_l); + write32(base + NvRegMacAddrB, mac_h); +#else + /* Set that into NIC. */ + pci_write_config32(dev, 0xa8, mac_l); + pci_write_config32(dev, 0xac, mac_h); +#endif + + nic_index++; + +#if CONFIG_PCI_ROM_RUN == 1 + pci_dev_init(dev); /* It will init Option ROM. */ +#endif +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver nic_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, +}; + +static const struct pci_driver nic_bridge_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, +}; diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c new file mode 100644 index 0000000000..044c7100d4 --- /dev/null +++ b/src/southbridge/nvidia/ck804/pci.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "ck804.h" + +static void pci_init(struct device *dev) +{ + uint32_t dword; + device_t pci_domain_dev; + struct resource *mem, *pref; + + dword = pci_read_config32(dev, 0x04); + dword |= (1 << 8); /* System error enable */ + dword |= (1 << 30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + +#if 0 + word = pci_read_config16(dev, 0x48); + word |= (1 << 0); /* MRL2MRM */ + word |= (1 << 2); /* MR2MRM */ + pci_write_config16(dev, 0x48, word); +#endif + +#if 1 + dword = pci_read_config32(dev, 0x4c); + dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ + pci_write_config32(dev, 0x4c, dword); +#endif + + pci_domain_dev = dev->bus->dev; + while (pci_domain_dev) { + if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) + break; + pci_domain_dev = pci_domain_dev->bus->dev; + } + + if (!pci_domain_dev) + return; /* Impossible */ + + pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); + mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); + + if (!mem) + return; /* Impossible */ + + if (!pref || pref->base > mem->base) { + dword = mem->base & (0xffff0000UL); + printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); + } else { + dword = pref->base & (0xffff0000UL); + printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); + } + + printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); + pci_write_config32(dev, 0x50, dword); /* TOM */ +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + // .enable = ck804_enable, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, +}; diff --git a/src/southbridge/nvidia/ck804/pcie.c b/src/southbridge/nvidia/ck804/pcie.c new file mode 100644 index 0000000000..cbde9cf57c --- /dev/null +++ b/src/southbridge/nvidia/ck804/pcie.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void pcie_init(struct device *dev) +{ + uint32_t dword; + + /* Enable PCI error detecting. */ + dword = pci_read_config32(dev, 0x04); + dword |= (1 << 8); /* System error enable */ + dword |= (1 << 30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); +} + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + // .enable = ck804_enable, +}; + +static const struct pci_driver pcie_driver __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, +}; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c new file mode 100644 index 0000000000..7f73e68d35 --- /dev/null +++ b/src/southbridge/nvidia/ck804/reset.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) + +typedef unsigned device_t; + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = (dev >> 4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = (dev >> 4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9. */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c new file mode 100644 index 0000000000..b3ec80422d --- /dev/null +++ b/src/southbridge/nvidia/ck804/sata.c @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "ck804.h" + +#ifndef CK804_SATA_RESET_FOR_ATAPI +#define CK804_SATA_RESET_FOR_ATAPI 0 +#endif + +#if CK804_SATA_RESET_FOR_ATAPI +static void sata_com_reset(struct device *dev, unsigned reset) +// reset = 1 : reset +// reset = 0 : clear +{ + uint32_t *base; + uint32_t dword; + int loop; + + base = (uint32_t *) pci_read_config32(dev, 0x24); + + printk(BIOS_DEBUG, "base = %08lx\n", base); + + if (reset) { + *(base + 4) = 0xffffffff; + *(base + 0x44) = 0xffffffff; + } + + dword = *(base + 8); + dword &= ~(0xf); + dword |= reset; + + *(base + 8) = dword; + *(base + 0x48) = dword; + +#if 0 + udelay(1000); + dword &= ~(0xf); + *(base + 8) = dword; + *(base + 0x48) = dword; +#endif + + if (reset) + return; + + dword = *(base + 0); + printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); + if (dword == 0x113) { + loop = 200000; // 2 + do { + dword = *(base + 4); + if ((dword & 0x10000) != 0) + break; + udelay(10); + } while (--loop > 0); + printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); + } + + dword = *(base + 0x40); + printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); + if (dword == 0x113) { + loop = 200000; //2 + do { + dword = *(base + 0x44); + if ((dword & 0x10000) != 0) + break; + udelay(10); + } while (--loop > 0); + printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); + } +} +#endif + +static void sata_init(struct device *dev) +{ + uint32_t dword; + struct southbridge_nvidia_ck804_config *conf; + + conf = dev->chip_info; + + dword = pci_read_config32(dev, 0x50); + /* Ensure prefetch is disabled. */ + dword &= ~((1 << 15) | (1 << 13)); + if (conf->sata1_enable) { + /* Enable secondary SATA interface. */ + dword |= (1 << 0); + printk(BIOS_DEBUG, "SATA S \t"); + } + if (conf->sata0_enable) { + /* Enable primary SATA interface. */ + dword |= (1 << 1); + printk(BIOS_DEBUG, "SATA P \n"); + } +#if 0 + /* Write back */ + dword |= (1 << 12); + dword |= (1 << 14); +#endif + +#if 0 + /* ADMA */ + dword |= (1 << 16); + dword |= (1 << 17); +#endif + +#if 1 + /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ + dword &= ~(0x1f << 24); + dword |= (0x15 << 24); +#endif + pci_write_config32(dev, 0x50, dword); + +#if 0 + /* SLUMBER_DURING_D3 */ + dword = pci_read_config32(dev, 0x7c); + dword &= ~(1 << 4); + pci_write_config32(dev, 0x7c, dword); + + dword = pci_read_config32(dev, 0xd0); + dword &= ~(0xff << 24); + dword |= (0x68 << 24); + pci_write_config32(dev, 0xd0, dword); + + dword = pci_read_config32(dev, 0xe0); + dword &= ~(0xff << 24); + dword |= (0x68 << 24); + pci_write_config32(dev, 0xe0, dword); +#endif + + dword = pci_read_config32(dev, 0xf8); + dword |= 2; + pci_write_config32(dev, 0xf8, dword); + +#if CK804_SATA_RESET_FOR_ATAPI + dword = pci_read_config32(dev, 0xac); + dword &= ~((1 << 13) | (1 << 14)); + dword |= (1 << 13) | (0 << 14); + pci_write_config32(dev, 0xac, dword); + + sata_com_reset(dev, 1); /* For discover some s-atapi device. */ +#endif + +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + // .enable = ck804_enable, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0, +}; + +static const struct pci_driver sata1_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, +}; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c new file mode 100644 index 0000000000..b1c6e28530 --- /dev/null +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ck804.h" +#include "smbus.h" + +static int lsmbus_recv_byte(device_t dev) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); + + return do_smbus_recv_byte(res->base, device); +} + +static int lsmbus_send_byte(device_t dev, uint8_t val) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); + + return do_smbus_send_byte(res->base, device, val); +} + +static int lsmbus_read_byte(device_t dev, uint8_t address) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); + + return do_smbus_write_byte(res->base, device, address, val); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, + .ops_smbus_bus = &lops_smbus_bus, +}; + +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, +}; diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h new file mode 100644 index 0000000000..2cdcadce80 --- /dev/null +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#define SMBHSTSTAT 0x1 +#define SMBHSTPRTCL 0x0 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x2 +#define SMBHSTDAT0 0x4 +#define SMBHSTDAT1 0x5 + +/* + * Between 1-10 seconds, We should never timeout normally. + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100 * 1000 * 10) + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +#if 0 +/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ +static int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) + return 0; + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + return -2; +} +#endif + +static int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + if ((val & 0xff) != 0) + return 0; + } while (--loops); + return -3; +} + +#ifndef __PRE_RAM__ +static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +{ + unsigned char global_status_register, byte; + +#if 0 + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) + return -2; +#endif + + /* Set the device I'm talking to. */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* Set the command/address. */ + outb(0, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* Byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) + return -3; + + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; + + /* Read results of transaction. */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + /* Lose check, otherwise it should be 0. */ + if (global_status_register != 0x80) + return -1; + + return byte; +} + +static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, + unsigned char val) +{ + unsigned global_status_register; + +#if 0 + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) + return -2; +#endif + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* Set the device I'm talking to. */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(0, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* Set up for a byte data write. */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) + return -3; + + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; + + if (global_status_register != 0x80) + return -1; + + return 0; +} +#endif + +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, + unsigned address) +{ + unsigned char global_status_register, byte; + +#if 0 + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) + return -2; +#endif + + /* Set the device I'm talking to. */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* Set the command/address. */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* Byte data read */ + outb(0x07, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) + return -3; + + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; + + /* Read results of transaction. */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + /* Lose check, otherwise it should be 0. */ + if (global_status_register != 0x80) + return -1; + + return byte; +} + +static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, + unsigned address, unsigned char val) +{ + unsigned global_status_register; + +#if 0 + /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ + if (smbus_wait_until_ready(smbus_io_base) < 0) + return -2; +#endif + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* Set the device I'm talking to. */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* Set up for a byte data write. */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* Poll for transaction completion. */ + if (smbus_wait_until_done(smbus_io_base) < 0) + return -3; + + /* Lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; + + if (global_status_register != 0x80) + return -1; + + return 0; +} diff --git a/src/southbridge/nvidia/ck804/usb.c b/src/southbridge/nvidia/ck804/usb.c new file mode 100644 index 0000000000..45ee734eb1 --- /dev/null +++ b/src/southbridge/nvidia/ck804/usb.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void usb1_init(struct device *dev) +{ + struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; + if (conf->usb1_hc_reset) { + /* + * Somehow the warm reset does not really reset the USB + * controller. Later, during boot, when the Bus Master bit is + * set, the USB controller trashes the memory, causing weird + * misbehavior. Was detected on Sun Ultra40, where mptable + * was damaged. + */ + uint32_t bar0 = pci_read_config32(dev, 0x10); + uint32_t *regs = (uint32_t *) (bar0 & ~0xfff); + + /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ + regs[2] |= 1; + } +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb1_init, + // .enable = ck804_enable, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver usb_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, +}; diff --git a/src/southbridge/nvidia/ck804/usb2.c b/src/southbridge/nvidia/ck804/usb2.c new file mode 100644 index 0000000000..e53f38f019 --- /dev/null +++ b/src/southbridge/nvidia/ck804/usb2.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void usb2_init(struct device *dev) +{ + uint32_t dword; + dword = pci_read_config32(dev, 0xf8); + dword |= 40; + pci_write_config32(dev, 0xf8, dword); +} + +static struct device_operations usb2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb2_init, + // .enable = ck804_enable, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, +}; + +static const struct pci_driver usb2_driver __pci_driver = { + .ops = &usb2_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_USB2, +}; -- cgit v1.2.3