From c02b4fc9db3c3c1e263027382697b566127f66bb Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 22 Mar 2010 11:42:32 +0000 Subject: printk_foo -> printk(BIOS_FOO, ...) Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/nvidia/ck804/ck804_fadt.c | 2 +- src/southbridge/nvidia/ck804/ck804_ide.c | 4 ++-- src/southbridge/nvidia/ck804/ck804_lpc.c | 10 +++++----- src/southbridge/nvidia/ck804/ck804_pci.c | 6 +++--- src/southbridge/nvidia/ck804/ck804_sata.c | 14 +++++++------- 5 files changed, 18 insertions(+), 18 deletions(-) (limited to 'src/southbridge/nvidia/ck804') diff --git a/src/southbridge/nvidia/ck804/ck804_fadt.c b/src/southbridge/nvidia/ck804/ck804_fadt.c index 1bfc22d915..205f1f0550 100644 --- a/src/southbridge/nvidia/ck804/ck804_fadt.c +++ b/src/southbridge/nvidia/ck804/ck804_fadt.c @@ -13,7 +13,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - printk_debug("pm_base: 0x%04x\n", pm_base); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/nvidia/ck804/ck804_ide.c b/src/southbridge/nvidia/ck804/ck804_ide.c index df4659c228..f46a057ef7 100644 --- a/src/southbridge/nvidia/ck804/ck804_ide.c +++ b/src/southbridge/nvidia/ck804/ck804_ide.c @@ -25,12 +25,12 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary IDE interface. */ word |= (1 << 0); - printk_debug("IDE1 \t"); + printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { /* Enable primary IDE interface. */ word |= (1 << 1); - printk_debug("IDE0\n"); + printk(BIOS_DEBUG, "IDE0\n"); } word |= (1 << 12); diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index 2b840fcbdd..d68a5b1077 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -95,7 +95,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev, 0x44, 0xfed00001); hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; - printk_debug("Enabling HPET @0x%lx\n", hpet_address); + printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); } unsigned pm_base=0; @@ -108,7 +108,7 @@ static void lpc_init(device_t dev) lpc_common_init(dev); pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk_info("%s: pm_base = %x \n", __func__, pm_base); + printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); #if CK804_CHIP_REV==1 if (dev->bus->secondary != 1) @@ -129,7 +129,7 @@ static void lpc_init(device_t dev) if (!on) byte |= 0x40; pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); /* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; @@ -141,7 +141,7 @@ static void lpc_init(device_t dev) outl(((on << 1) + 0x10), (pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8 - on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } #if 0 @@ -250,7 +250,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); + printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c index 70ccdc6329..ccbbbd48a9 100644 --- a/src/southbridge/nvidia/ck804/ck804_pci.c +++ b/src/southbridge/nvidia/ck804/ck804_pci.c @@ -53,13 +53,13 @@ static void pci_init(struct device *dev) if (!pref || pref->base > mem->base) { dword = mem->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); + printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { dword = pref->base & (0xffff0000UL); - printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); + printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } - printk_debug("[0x50] <-- 0x%08x\n", dword); + printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); pci_write_config32(dev, 0x50, dword); /* TOM */ } diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c index e9218abf3a..8eed906ce8 100644 --- a/src/southbridge/nvidia/ck804/ck804_sata.c +++ b/src/southbridge/nvidia/ck804/ck804_sata.c @@ -26,7 +26,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) base = (uint32_t *) pci_read_config32(dev, 0x24); - printk_debug("base = %08lx\n", base); + printk(BIOS_DEBUG, "base = %08lx\n", base); if (reset) { *(base + 4) = 0xffffffff; @@ -51,7 +51,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) return; dword = *(base + 0); - printk_debug("*(base+0)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword); if (dword == 0x113) { loop = 200000; // 2 do { @@ -60,11 +60,11 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword); } dword = *(base + 0x40); - printk_debug("*(base+0x40)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword); if (dword == 0x113) { loop = 200000; //2 do { @@ -73,7 +73,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword); } } #endif @@ -91,12 +91,12 @@ static void sata_init(struct device *dev) if (conf->sata1_enable) { /* Enable secondary SATA interface. */ dword |= (1 << 0); - printk_debug("SATA S \t"); + printk(BIOS_DEBUG, "SATA S \t"); } if (conf->sata0_enable) { /* Enable primary SATA interface. */ dword |= (1 << 1); - printk_debug("SATA P \n"); + printk(BIOS_DEBUG, "SATA P \n"); } #if 0 /* Write back */ -- cgit v1.2.3