From d1a0c5770803e45dabecf6094fccb9895ea76d10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 30 Jul 2017 11:37:14 +0300 Subject: usbdebug: Consolidate EHCI_BAR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/southbridge/nvidia/ck804/enable_usbdebug.c | 5 ----- src/southbridge/nvidia/mcp55/enable_usbdebug.c | 5 ----- 2 files changed, 10 deletions(-) (limited to 'src/southbridge/nvidia') diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 0f0e4cddbc..4ae4aa0052 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, base); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index dfeb351b67..679a71d7b3 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, base); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } -- cgit v1.2.3