From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/via/vt8235/Makefile.inc | 8 +- src/southbridge/via/vt8235/early_serial.c | 77 +++++++ src/southbridge/via/vt8235/early_smbus.c | 249 +++++++++++++++++++++ src/southbridge/via/vt8235/ide.c | 113 ++++++++++ src/southbridge/via/vt8235/lpc.c | 261 +++++++++++++++++++++++ src/southbridge/via/vt8235/nic.c | 36 ++++ src/southbridge/via/vt8235/usb.c | 44 ++++ src/southbridge/via/vt8235/vt8235_early_serial.c | 77 ------- src/southbridge/via/vt8235/vt8235_early_smbus.c | 249 --------------------- src/southbridge/via/vt8235/vt8235_ide.c | 113 ---------- src/southbridge/via/vt8235/vt8235_lpc.c | 261 ----------------------- src/southbridge/via/vt8235/vt8235_nic.c | 36 ---- src/southbridge/via/vt8235/vt8235_usb.c | 44 ---- 13 files changed, 784 insertions(+), 784 deletions(-) create mode 100644 src/southbridge/via/vt8235/early_serial.c create mode 100644 src/southbridge/via/vt8235/early_smbus.c create mode 100644 src/southbridge/via/vt8235/ide.c create mode 100644 src/southbridge/via/vt8235/lpc.c create mode 100644 src/southbridge/via/vt8235/nic.c create mode 100644 src/southbridge/via/vt8235/usb.c delete mode 100644 src/southbridge/via/vt8235/vt8235_early_serial.c delete mode 100644 src/southbridge/via/vt8235/vt8235_early_smbus.c delete mode 100644 src/southbridge/via/vt8235/vt8235_ide.c delete mode 100644 src/southbridge/via/vt8235/vt8235_lpc.c delete mode 100644 src/southbridge/via/vt8235/vt8235_nic.c delete mode 100644 src/southbridge/via/vt8235/vt8235_usb.c (limited to 'src/southbridge/via/vt8235') diff --git a/src/southbridge/via/vt8235/Makefile.inc b/src/southbridge/via/vt8235/Makefile.inc index 06d533560b..02e22640bf 100644 --- a/src/southbridge/via/vt8235/Makefile.inc +++ b/src/southbridge/via/vt8235/Makefile.inc @@ -18,7 +18,7 @@ ## driver-y += vt8235.c -driver-y += vt8235_ide.c -driver-y += vt8235_lpc.c -driver-y += vt8235_nic.c -driver-y += vt8235_usb.c +driver-y += ide.c +driver-y += lpc.c +driver-y += nic.c +driver-y += usb.c diff --git a/src/southbridge/via/vt8235/early_serial.c b/src/southbridge/via/vt8235/early_serial.c new file mode 100644 index 0000000000..11f98fae39 --- /dev/null +++ b/src/southbridge/via/vt8235/early_serial.c @@ -0,0 +1,77 @@ +/* + * Enable the serial evices on the VIA + */ + + +/* The base address is 0x15c, 0x2e, depending on config bytes */ + +#define SIO_BASE 0x3f0 +#define SIO_DATA SIO_BASE+1 + +static void vt8235_writepnpaddr(uint8_t val) +{ + outb(val, 0x2e); + outb(val, 0xeb); +} + +static void vt8235_writepnpdata(uint8_t val) +{ + outb(val, 0x2f); + outb(val, 0xeb); +} + + +static void vt8235_writesiobyte(uint16_t reg, uint8_t val) +{ + outb(val, reg); +} + +static void vt8235_writesioword(uint16_t reg, uint16_t val) +{ + outw(val, reg); +} + + +/* regs we use: 85, and the southbridge devfn is defined by the + mainboard + */ + +static void enable_vt8235_serial(void) +{ + // turn on pnp + vt8235_writepnpaddr(0x87); + vt8235_writepnpaddr(0x87); + // now go ahead and set up com1. + // set address + vt8235_writepnpaddr(0x7); + vt8235_writepnpdata(0x2); + // enable serial out + vt8235_writepnpaddr(0x30); + vt8235_writepnpdata(0x1); + // serial port 1 base address (FEh) + vt8235_writepnpaddr(0x60); + vt8235_writepnpdata(0xfe); + // serial port 1 IRQ (04h) + vt8235_writepnpaddr(0x70); + vt8235_writepnpdata(0x4); + // serial port 1 control + vt8235_writepnpaddr(0xf0); + vt8235_writepnpdata(0x2); + // turn of pnp + vt8235_writepnpaddr(0xaa); + + // set up reg to set baud rate. + vt8235_writesiobyte(0x3fb, 0x80); + // Set 115 kb + vt8235_writesioword(0x3f8, 1); + // Set 9.6 kb + // WRITESIOWORD(0x3f8, 12) + // now set no parity, one stop, 8 bits + vt8235_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + vt8235_writesiobyte(0x3fc, 3); + // Enable interrupts + vt8235_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + vt8235_writesiobyte(0x3f8, 48); +} diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c new file mode 100644 index 0000000000..d091099fdb --- /dev/null +++ b/src/southbridge/via/vt8235/early_smbus.c @@ -0,0 +1,249 @@ +#define SMBUS_IO_BASE 0xf00 + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBSLVCTL 0x8 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +/* Define register settings */ +#define HOST_RESET 0xff +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ + + +#define SMBUS_TIMEOUT (100*1000*10) + +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +static void enable_smbus(void) +{ + device_t dev; + unsigned char c; + int i; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8235), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + } + + // set IO base address to SMBUS_IO_BASE + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); + + // Enable SMBus + pci_write_config8(dev, 0xd2, (0x4 << 1) | 1); + + /* make it work for I/O ... + */ + pci_write_config16(dev, 4, 1); + + /* FIX for half baud rate problem */ + /* let clocks and the like settle */ + /* as yet arbitrary count - 1000 is too little 5000 works */ + for(i = 0 ; i < 5000 ; i++) + outb(0x80,0x80); + + /* + * The VT1211 serial port needs 48 mhz clock, on power up it is getting + * only 24 mhz, there is some mysterious device on the smbus that can + * fix this...this code below does it. + * */ + outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); + outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); + outb(0x83, SMBUS_IO_BASE+SMBHSTCMD); + outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD); + outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL); + + for (;;) { + c = inb(SMBUS_IO_BASE+SMBHSTSTAT); + if ((c & 1) == 0) + break; + } +} + + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned char c; + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + smbus_delay(); + c = inb(SMBUS_IO_BASE + SMBHSTSTAT); + while((c & 1) == 1) { + print_debug("c is "); + print_debug_hex8(c); + print_debug("\n"); + c = inb(SMBUS_IO_BASE + SMBHSTSTAT); + /* nop */ + } + + } while(--loops); + return loops?0:-1; +} + +void smbus_reset(void) +{ + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_wait_until_ready(); + print_debug("After reset status "); + print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); + print_debug("\n"); +} + + + +static int smbus_wait_until_done(void) +{ + unsigned long loops; + unsigned char byte; + loops = SMBUS_TIMEOUT; + do { + smbus_delay(); + + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if (byte & 1) + break; + + } while(--loops); + return loops?0:-1; +} + +static void smbus_print_error(unsigned char host_status_register) +{ + + print_err("smbus_error: "); + print_err_hex8(host_status_register); + print_err("\n"); + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + print_err("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\n"); + } +} + + +/* SMBus routines borrowed from VIA's Trident Driver */ +/* this works, so I am not going to touch it for now -- rgm */ +static unsigned char smbus_read_byte(unsigned char devAdr, + unsigned char bIndex) +{ + unsigned short i; + unsigned char bData; + unsigned char sts = 0; + + /* clear host status */ + outb(0xff, SMBUS_IO_BASE); + + /* check SMBUS ready */ + for ( i = 0; i < 0xFFFF; i++ ) + if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) + break; + + /* set host command */ + outb(bIndex, SMBUS_IO_BASE+3); + + /* set slave address */ + outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4); + + /* start */ + outb(0x48, SMBUS_IO_BASE+2); + + /* SMBUS Wait Ready */ + for ( i = 0; i < 0xFFFF; i++ ) + if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 ) + break; + + if ((sts & ~3) != 0) { + smbus_print_error(sts); + return 0; + } + bData=inb(SMBUS_IO_BASE+5); + + return bData; + +} + +/* for reference, here is the fancier version which we will use at some + * point + */ +# if 0 +int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) +{ + unsigned char host_status_register; + unsigned char byte; + + reset(); + + smbus_wait_until_ready(); + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); + + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the In Use Status... */ + host_status_register &= ~(1 << 6); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + smbus_print_error(byte); + + *result = byte; + return host_status_register != 0x02; +} + + +#endif + diff --git a/src/southbridge/via/vt8235/ide.c b/src/southbridge/via/vt8235/ide.c new file mode 100644 index 0000000000..961f860fed --- /dev/null +++ b/src/southbridge/via/vt8235/ide.c @@ -0,0 +1,113 @@ +#include +#include +#include +#include +#include +#include "chip.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8235_config *conf = dev->chip_info; + unsigned char enables; + + printk(BIOS_INFO, "Enabling VIA IDE.\n"); + + /*if (!conf->enable_native_ide) { */ + /* + * Run the IDE controller in 'compatiblity mode - i.e. don't + * use PCI interrupts. Using PCI ints confuses linux for some + * reason. + */ + printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", + __func__); + enables = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev, 0x42, enables); + enables = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", + enables); + /* } */ + + enables = pci_read_config8(dev, 0x40); + printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config8(dev, 0x40, enables); + enables = pci_read_config8(dev, 0x40); + printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + enables = pci_read_config8(dev, 0x41); + enables |= 0xf0; + pci_write_config8(dev, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev, 0x9); + printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config8(dev, 0x9, enables); + enables = pci_read_config8(dev, 0x9); + printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev, 0x4); + printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config8(dev, 0x4, enables); + enables = pci_read_config8(dev, 0x4); + printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); + + if (!conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config32(dev, 0x10, 0x0); + pci_write_config32(dev, 0x14, 0x0); + pci_write_config32(dev, 0x18, 0x0); + pci_write_config32(dev, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev, 0x3d, 0x0); + pci_write_config8(dev, 0x3c, 0xff); + } +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c new file mode 100644 index 0000000000..b355ad0d88 --- /dev/null +++ b/src/southbridge/via/vt8235/lpc.c @@ -0,0 +1,261 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. + This is how the Award bios sets it up too. + epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then + make sure that ACPI dsdt is changed to suit. + + IRQ 0 = timer + IRQ 1 = keyboard + IRQ 2 = cascade + IRQ 3 = COM 2 + IRQ 4 = COM 1 + IRQ 5 = available for PCI interrupts + IRQ 6 = floppy or availbale for PCI if floppy controller disabled + IRQ 7 = LPT or available if LPT port disabled + IRQ 8 = rtc + IRQ 9 = available for PCI interrupts + IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia) + IRQ 11 = cardbus slot or available for PCI if no cardbus (ie epia) + IRQ 12 = PS2 mouse (hardwired to 12) + IRQ 13 = legacy FPU interrupt + IRQ 14 = IDE controller 1 + IRQ 15 = IDE controller 2 + +*/ +static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 }; + +static const unsigned char usbPins[4] = { 'A','B','C','D'}; +static const unsigned char enetPins[4] = { 'A','B','C','D'}; +static const unsigned char slotPins[4] = { 'B','C','D','A'}; +static const unsigned char firewirePins[4] = { 'B','C','D','A'}; +static const unsigned char vt8235Pins[4] = { 'A','B','C','D'}; +static const unsigned char vgaPins[4] = { 'A','B','C','D'}; +static const unsigned char cbPins[4] = { 'A','B','C','D'}; +static const unsigned char riserPins[4] = { 'A','B','C','D'}; + + +static unsigned char *pin_to_irq(const unsigned char *pin) +{ + static unsigned char Irqs[4]; + int i; + for (i = 0 ; i < 4 ; i++) + Irqs[i] = pciIrqs[ pin[i] - 'A' ]; + + return Irqs; +} + +static void pci_routing_fixup(struct device *dev) +{ + printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); + + /* set up PCI IRQ routing */ + pci_write_config8(dev, 0x55, pciIrqs[0] << 4); + pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); + pci_write_config8(dev, 0x57, pciIrqs[3] << 4); + + + // firewire built into southbridge + printk(BIOS_INFO, "setting firewire\n"); + pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins)); + + // Standard usb components + printk(BIOS_INFO, "setting usb\n"); + pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); + + // VT8235 + sound hardware + printk(BIOS_INFO, "setting vt8235\n"); + pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins)); + + // Ethernet built into southbridge + printk(BIOS_INFO, "setting ethernet\n"); + pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); + + // VGA + printk(BIOS_INFO, "setting vga\n"); + pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); + + // PCI slot + printk(BIOS_INFO, "setting pci slot\n"); + pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); + + // Cardbus slot + printk(BIOS_INFO, "setting cardbus slot\n"); + pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); + + // Via 2 slot riser card 2nd slot + printk(BIOS_INFO, "setting riser slot\n"); + pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); + + printk(BIOS_SPEW, "%s: DONE\n", __func__); +} + +/* + * Set up the power management capabilities directly into ACPI mode. This + * avoids having to handle any System Management Interrupts (SMI's) which I + * can't figure out how to do !!!! + */ + +static void setup_pm(device_t dev) +{ + // Set gen config 0 + pci_write_config8(dev, 0x80, 0x20); + + // Set ACPI base address to IO 0x400 + pci_write_config16(dev, 0x88, 0x0401); + + // set ACPI irq to 5 + pci_write_config8(dev, 0x82, 0x45); + + // primary interupt channel + pci_write_config16(dev, 0x84, 0x30f2); + + // throttle / stop clock control + pci_write_config8(dev, 0x8d, 0x18); + + pci_write_config8(dev, 0x93, 0x88); + pci_write_config8(dev, 0x94, 0xb0); + pci_write_config8(dev, 0x95, 0xc0); + pci_write_config8(dev, 0x98, 0); + pci_write_config8(dev, 0x99, 0xea); + pci_write_config8(dev, 0xe4, 0x14); + pci_write_config8(dev, 0xe5, 0x08); + + + // Enable ACPI access (and setup like award) + pci_write_config8(dev, 0x81, 0x84); + + outw(0xffff, 0x400); + outw(0xffff, 0x420); + outw(0xffff, 0x428); + outl(0xffffffff, 0x430); + + outw(0x0, 0x424); + outw(0x0, 0x42a); + outw(0x1, 0x42c); + outl(0x0, 0x434); + outl(0x01, 0x438); + outb(0x0, 0x442); + outl(0xffff7fff, 0x448); + outw(0x001, 0x404); +} + +static void vt8235_init(struct device *dev) +{ + unsigned char enables; + + printk(BIOS_DEBUG, "vt8235 init\n"); + + // enable the internal I/O decode + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + // Map 4MB of FLASH into the address space + pci_write_config8(dev, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev, 0x40); + enables |= 0x45; + pci_write_config8(dev, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config8(dev, 0x42); + enables |= 0xf0; + pci_write_config8(dev, 0x42, enables); + + /* Set 0x58 to 0x03 to match Award */ + pci_write_config8(dev, 0x58, 0x03); + + /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config8(dev, 0x4a); + enables |= 0x08; + pci_write_config8(dev, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config8(dev, 0x58, 0x03); + + + /* enable serial irq */ + pci_write_config8(dev, 0x52, 0x9); + + /* dma */ + pci_write_config8(dev, 0x53, 0x00); + + // Power management setup + setup_pm(dev); + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev, 0x40, 0x54); + + // Start the rtc + rtc_init(0); +} + +/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this + device has a resource to set - so set a dummy one */ +static void vt8235_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void vt8235_set_resources(device_t dev) +{ + //struct resource *resource; + //resource = find_resource(dev,1); + //resource->flags |= IORESOURCE_STORED; + pci_dev_set_resources(dev); +} + +static void southbridge_init(struct device *dev) +{ + vt8235_init(dev); + pci_routing_fixup(dev); +} + +static struct device_operations vt8235_lpc_ops = { + .read_resources = vt8235_read_resources, + .set_resources = vt8235_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = southbridge_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &vt8235_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8235, +}; diff --git a/src/southbridge/via/vt8235/nic.c b/src/southbridge/via/vt8235/nic.c new file mode 100644 index 0000000000..71f169c055 --- /dev/null +++ b/src/southbridge/via/vt8235/nic.c @@ -0,0 +1,36 @@ +#include +#include +#include +#include +#include + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +static void nic_init(struct device *dev) +{ + uint8_t byte; + + printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8233_7, +}; diff --git a/src/southbridge/via/vt8235/usb.c b/src/southbridge/via/vt8235/usb.c new file mode 100644 index 0000000000..c712136c72 --- /dev/null +++ b/src/southbridge/via/vt8235/usb.c @@ -0,0 +1,44 @@ +#include +#include +#include +#include +#include + +/* really nothing to do here, both usb 1.1 & 2.0 are normal PCI devices and so get resources allocated + properly. They are part of the southbridge and are enabled in the chip enable function for the southbridge */ + +static void usb_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n"); + + /* pci_write_config8(dev, 0x04, 0x07); */ + + /* + * To disable; though do we need to do this? + pci_write_config8(dev1, 0x3c, 0x00); + pci_write_config8(dev1, 0x04, 0x00); + + Also, on the root dev, for enable: + regval = pci_read_config8(dev0, 0x50); + regval &= ~(0x36); + pci_write_config8(dev0, 0x50, regval); + + (regval |= 0x36; for disable) + */ +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_2, +}; + diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c deleted file mode 100644 index 11f98fae39..0000000000 --- a/src/southbridge/via/vt8235/vt8235_early_serial.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Enable the serial evices on the VIA - */ - - -/* The base address is 0x15c, 0x2e, depending on config bytes */ - -#define SIO_BASE 0x3f0 -#define SIO_DATA SIO_BASE+1 - -static void vt8235_writepnpaddr(uint8_t val) -{ - outb(val, 0x2e); - outb(val, 0xeb); -} - -static void vt8235_writepnpdata(uint8_t val) -{ - outb(val, 0x2f); - outb(val, 0xeb); -} - - -static void vt8235_writesiobyte(uint16_t reg, uint8_t val) -{ - outb(val, reg); -} - -static void vt8235_writesioword(uint16_t reg, uint16_t val) -{ - outw(val, reg); -} - - -/* regs we use: 85, and the southbridge devfn is defined by the - mainboard - */ - -static void enable_vt8235_serial(void) -{ - // turn on pnp - vt8235_writepnpaddr(0x87); - vt8235_writepnpaddr(0x87); - // now go ahead and set up com1. - // set address - vt8235_writepnpaddr(0x7); - vt8235_writepnpdata(0x2); - // enable serial out - vt8235_writepnpaddr(0x30); - vt8235_writepnpdata(0x1); - // serial port 1 base address (FEh) - vt8235_writepnpaddr(0x60); - vt8235_writepnpdata(0xfe); - // serial port 1 IRQ (04h) - vt8235_writepnpaddr(0x70); - vt8235_writepnpdata(0x4); - // serial port 1 control - vt8235_writepnpaddr(0xf0); - vt8235_writepnpdata(0x2); - // turn of pnp - vt8235_writepnpaddr(0xaa); - - // set up reg to set baud rate. - vt8235_writesiobyte(0x3fb, 0x80); - // Set 115 kb - vt8235_writesioword(0x3f8, 1); - // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) - // now set no parity, one stop, 8 bits - vt8235_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - vt8235_writesiobyte(0x3fc, 3); - // Enable interrupts - vt8235_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - vt8235_writesiobyte(0x3f8, 48); -} diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c deleted file mode 100644 index d091099fdb..0000000000 --- a/src/southbridge/via/vt8235/vt8235_early_smbus.c +++ /dev/null @@ -1,249 +0,0 @@ -#define SMBUS_IO_BASE 0xf00 - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBSLVCTL 0x8 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -/* Define register settings */ -#define HOST_RESET 0xff -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ - - -#define SMBUS_TIMEOUT (100*1000*10) - -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 - -static void enable_smbus(void) -{ - device_t dev; - unsigned char c; - int i; - - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8235), 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - - // set IO base address to SMBUS_IO_BASE - pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); - - // Enable SMBus - pci_write_config8(dev, 0xd2, (0x4 << 1) | 1); - - /* make it work for I/O ... - */ - pci_write_config16(dev, 4, 1); - - /* FIX for half baud rate problem */ - /* let clocks and the like settle */ - /* as yet arbitrary count - 1000 is too little 5000 works */ - for(i = 0 ; i < 5000 ; i++) - outb(0x80,0x80); - - /* - * The VT1211 serial port needs 48 mhz clock, on power up it is getting - * only 24 mhz, there is some mysterious device on the smbus that can - * fix this...this code below does it. - * */ - outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); - outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); - outb(0x83, SMBUS_IO_BASE+SMBHSTCMD); - outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD); - outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL); - - for (;;) { - c = inb(SMBUS_IO_BASE+SMBHSTSTAT); - if ((c & 1) == 0) - break; - } -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(void) -{ - unsigned char c; - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - smbus_delay(); - c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - while((c & 1) == 1) { - print_debug("c is "); - print_debug_hex8(c); - print_debug("\n"); - c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - /* nop */ - } - - } while(--loops); - return loops?0:-1; -} - -void smbus_reset(void) -{ - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - - smbus_wait_until_ready(); - print_debug("After reset status "); - print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\n"); -} - - - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - unsigned char byte; - loops = SMBUS_TIMEOUT; - do { - smbus_delay(); - - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if (byte & 1) - break; - - } while(--loops); - return loops?0:-1; -} - -static void smbus_print_error(unsigned char host_status_register) -{ - - print_err("smbus_error: "); - print_err_hex8(host_status_register); - print_err("\n"); - if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); - } - if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); - } - if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); - } - if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\n"); - } - if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); - } -} - - -/* SMBus routines borrowed from VIA's Trident Driver */ -/* this works, so I am not going to touch it for now -- rgm */ -static unsigned char smbus_read_byte(unsigned char devAdr, - unsigned char bIndex) -{ - unsigned short i; - unsigned char bData; - unsigned char sts = 0; - - /* clear host status */ - outb(0xff, SMBUS_IO_BASE); - - /* check SMBUS ready */ - for ( i = 0; i < 0xFFFF; i++ ) - if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) - break; - - /* set host command */ - outb(bIndex, SMBUS_IO_BASE+3); - - /* set slave address */ - outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4); - - /* start */ - outb(0x48, SMBUS_IO_BASE+2); - - /* SMBUS Wait Ready */ - for ( i = 0; i < 0xFFFF; i++ ) - if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 ) - break; - - if ((sts & ~3) != 0) { - smbus_print_error(sts); - return 0; - } - bData=inb(SMBUS_IO_BASE+5); - - return bData; - -} - -/* for reference, here is the fancier version which we will use at some - * point - */ -# if 0 -int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) -{ - unsigned char host_status_register; - unsigned char byte; - - reset(); - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), - SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), - SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - host_status_register &= ~(1 << 6); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - smbus_print_error(byte); - - *result = byte; - return host_status_register != 0x02; -} - - -#endif - diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c deleted file mode 100644 index 961f860fed..0000000000 --- a/src/southbridge/via/vt8235/vt8235_ide.c +++ /dev/null @@ -1,113 +0,0 @@ -#include -#include -#include -#include -#include -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8235_config *conf = dev->chip_info; - unsigned char enables; - - printk(BIOS_INFO, "Enabling VIA IDE.\n"); - - /*if (!conf->enable_native_ide) { */ - /* - * Run the IDE controller in 'compatiblity mode - i.e. don't - * use PCI interrupts. Using PCI ints confuses linux for some - * reason. - */ - printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", - __func__); - enables = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); - enables &= ~0xc0; // compatability mode - pci_write_config8(dev, 0x42, enables); - enables = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", - enables); - /* } */ - - enables = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config8(dev, 0x40, enables); - enables = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); - - // Enable prefetch buffers - enables = pci_read_config8(dev, 0x41); - enables |= 0xf0; - pci_write_config8(dev, 0x41, enables); - - // Lower thresholds (cause award does it) - enables = pci_read_config8(dev, 0x43); - enables &= ~0x0f; - enables |= 0x05; - pci_write_config8(dev, 0x43, enables); - - // PIO read prefetch counter (cause award does it) - pci_write_config8(dev, 0x44, 0x18); - - // Use memory read multiple - pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. - // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when - // used in native mode - I've changed back to classic - enables = pci_read_config8(dev, 0x9); - printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - if (conf->enable_native_ide) { - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - } else { - enables &= ~0x5; - } - - pci_write_config8(dev, 0x9, enables); - enables = pci_read_config8(dev, 0x9); - printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - enables = pci_read_config8(dev, 0x4); - printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); - enables |= 7; - - // No need for stepping - kevinh@ispiri.com - enables &= ~0x80; - - pci_write_config8(dev, 0x4, enables); - enables = pci_read_config8(dev, 0x4); - printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); - - if (!conf->enable_native_ide) { - // Use compatability mode - per award bios - pci_write_config32(dev, 0x10, 0x0); - pci_write_config32(dev, 0x14, 0x0); - pci_write_config32(dev, 0x18, 0x0); - pci_write_config32(dev, 0x1c, 0x0); - - // Force interrupts to use compat mode - just like Award bios - pci_write_config8(dev, 0x3d, 0x0); - pci_write_config8(dev, 0x3c, 0xff); - } -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c deleted file mode 100644 index b355ad0d88..0000000000 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ /dev/null @@ -1,261 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - -/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. - This is how the Award bios sets it up too. - epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then - make sure that ACPI dsdt is changed to suit. - - IRQ 0 = timer - IRQ 1 = keyboard - IRQ 2 = cascade - IRQ 3 = COM 2 - IRQ 4 = COM 1 - IRQ 5 = available for PCI interrupts - IRQ 6 = floppy or availbale for PCI if floppy controller disabled - IRQ 7 = LPT or available if LPT port disabled - IRQ 8 = rtc - IRQ 9 = available for PCI interrupts - IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia) - IRQ 11 = cardbus slot or available for PCI if no cardbus (ie epia) - IRQ 12 = PS2 mouse (hardwired to 12) - IRQ 13 = legacy FPU interrupt - IRQ 14 = IDE controller 1 - IRQ 15 = IDE controller 2 - -*/ -static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 }; - -static const unsigned char usbPins[4] = { 'A','B','C','D'}; -static const unsigned char enetPins[4] = { 'A','B','C','D'}; -static const unsigned char slotPins[4] = { 'B','C','D','A'}; -static const unsigned char firewirePins[4] = { 'B','C','D','A'}; -static const unsigned char vt8235Pins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char cbPins[4] = { 'A','B','C','D'}; -static const unsigned char riserPins[4] = { 'A','B','C','D'}; - - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char Irqs[4]; - int i; - for (i = 0 ; i < 4 ; i++) - Irqs[i] = pciIrqs[ pin[i] - 'A' ]; - - return Irqs; -} - -static void pci_routing_fixup(struct device *dev) -{ - printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); - - /* set up PCI IRQ routing */ - pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); - pci_write_config8(dev, 0x57, pciIrqs[3] << 4); - - - // firewire built into southbridge - printk(BIOS_INFO, "setting firewire\n"); - pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins)); - - // Standard usb components - printk(BIOS_INFO, "setting usb\n"); - pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); - - // VT8235 + sound hardware - printk(BIOS_INFO, "setting vt8235\n"); - pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins)); - - // Ethernet built into southbridge - printk(BIOS_INFO, "setting ethernet\n"); - pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); - - // VGA - printk(BIOS_INFO, "setting vga\n"); - pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); - - // PCI slot - printk(BIOS_INFO, "setting pci slot\n"); - pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); - - // Cardbus slot - printk(BIOS_INFO, "setting cardbus slot\n"); - pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); - - // Via 2 slot riser card 2nd slot - printk(BIOS_INFO, "setting riser slot\n"); - pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); - - printk(BIOS_SPEW, "%s: DONE\n", __func__); -} - -/* - * Set up the power management capabilities directly into ACPI mode. This - * avoids having to handle any System Management Interrupts (SMI's) which I - * can't figure out how to do !!!! - */ - -static void setup_pm(device_t dev) -{ - // Set gen config 0 - pci_write_config8(dev, 0x80, 0x20); - - // Set ACPI base address to IO 0x400 - pci_write_config16(dev, 0x88, 0x0401); - - // set ACPI irq to 5 - pci_write_config8(dev, 0x82, 0x45); - - // primary interupt channel - pci_write_config16(dev, 0x84, 0x30f2); - - // throttle / stop clock control - pci_write_config8(dev, 0x8d, 0x18); - - pci_write_config8(dev, 0x93, 0x88); - pci_write_config8(dev, 0x94, 0xb0); - pci_write_config8(dev, 0x95, 0xc0); - pci_write_config8(dev, 0x98, 0); - pci_write_config8(dev, 0x99, 0xea); - pci_write_config8(dev, 0xe4, 0x14); - pci_write_config8(dev, 0xe5, 0x08); - - - // Enable ACPI access (and setup like award) - pci_write_config8(dev, 0x81, 0x84); - - outw(0xffff, 0x400); - outw(0xffff, 0x420); - outw(0xffff, 0x428); - outl(0xffffffff, 0x430); - - outw(0x0, 0x424); - outw(0x0, 0x42a); - outw(0x1, 0x42c); - outl(0x0, 0x434); - outl(0x01, 0x438); - outb(0x0, 0x442); - outl(0xffff7fff, 0x448); - outw(0x001, 0x404); -} - -static void vt8235_init(struct device *dev) -{ - unsigned char enables; - - printk(BIOS_DEBUG, "vt8235 init\n"); - - // enable the internal I/O decode - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - // Map 4MB of FLASH into the address space - pci_write_config8(dev, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev, 0x40); - enables |= 0x45; - pci_write_config8(dev, 0x40, enables); - - // Set 0x42 to 0xf0 to match Award bios - enables = pci_read_config8(dev, 0x42); - enables |= 0xf0; - pci_write_config8(dev, 0x42, enables); - - /* Set 0x58 to 0x03 to match Award */ - pci_write_config8(dev, 0x58, 0x03); - - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - // Set bit 3 of 0x4a, to match award (dummy pci request) - enables = pci_read_config8(dev, 0x4a); - enables |= 0x08; - pci_write_config8(dev, 0x4a, enables); - - // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - // Set 0x58 to 0x03 to match Award - pci_write_config8(dev, 0x58, 0x03); - - - /* enable serial irq */ - pci_write_config8(dev, 0x52, 0x9); - - /* dma */ - pci_write_config8(dev, 0x53, 0x00); - - // Power management setup - setup_pm(dev); - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev, 0x40, 0x54); - - // Start the rtc - rtc_init(0); -} - -/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this - device has a resource to set - so set a dummy one */ -static void vt8235_read_resources(device_t dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void vt8235_set_resources(device_t dev) -{ - //struct resource *resource; - //resource = find_resource(dev,1); - //resource->flags |= IORESOURCE_STORED; - pci_dev_set_resources(dev); -} - -static void southbridge_init(struct device *dev) -{ - vt8235_init(dev); - pci_routing_fixup(dev); -} - -static struct device_operations vt8235_lpc_ops = { - .read_resources = vt8235_read_resources, - .set_resources = vt8235_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = southbridge_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &vt8235_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8235, -}; diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c deleted file mode 100644 index 71f169c055..0000000000 --- a/src/southbridge/via/vt8235/vt8235_nic.c +++ /dev/null @@ -1,36 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * Enable the ethernet device and turn off stepping (because it is integrated - * inside the southbridge) - */ -static void nic_init(struct device *dev) -{ - uint8_t byte; - - printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n"); - - /* We don't need stepping - though the device supports it */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte &= ~PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/vt8235_usb.c deleted file mode 100644 index c712136c72..0000000000 --- a/src/southbridge/via/vt8235/vt8235_usb.c +++ /dev/null @@ -1,44 +0,0 @@ -#include -#include -#include -#include -#include - -/* really nothing to do here, both usb 1.1 & 2.0 are normal PCI devices and so get resources allocated - properly. They are part of the southbridge and are enabled in the chip enable function for the southbridge */ - -static void usb_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n"); - - /* pci_write_config8(dev, 0x04, 0x07); */ - - /* - * To disable; though do we need to do this? - pci_write_config8(dev1, 0x3c, 0x00); - pci_write_config8(dev1, 0x04, 0x00); - - Also, on the root dev, for enable: - regval = pci_read_config8(dev0, 0x50); - regval &= ~(0x36); - pci_write_config8(dev0, 0x50, regval); - - (regval |= 0x36; for disable) - */ -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_2, -}; - -- cgit v1.2.3