From 98236ca7844ec36bf1e43a9d689b55fa409f0a4a Mon Sep 17 00:00:00 2001 From: Florian Zumbiehl Date: Mon, 21 Nov 2011 03:10:47 +0100 Subject: make INT[EFGH]# of vt8237 configurable as gpio via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl Reviewed-on: http://review.coreboot.org/386 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek --- src/southbridge/via/vt8237r/lpc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/southbridge/via/vt8237r/lpc.c') diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 207dfdb335..43a9394bfa 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -421,10 +421,13 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; #if !CONFIG_EPIA_VT8237R_INIT unsigned char pwr_on; #endif + cfg = dev->chip_info; + /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); byte |= PCI_COMMAND_WAIT; @@ -509,7 +512,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->int_efgh_as_gpio) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } /* configure power state of the board after loss of power */ if (get_option(&pwr_on, "power_on_after_fail") < 0) -- cgit v1.2.3