From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/via/vt8237r/Makefile.inc | 14 +- src/southbridge/via/vt8237r/ctrl.c | 289 ++++++++++ src/southbridge/via/vt8237r/early_smbus.c | 498 +++++++++++++++++ src/southbridge/via/vt8237r/fadt.c | 173 ++++++ src/southbridge/via/vt8237r/ide.c | 132 +++++ src/southbridge/via/vt8237r/lpc.c | 624 ++++++++++++++++++++++ src/southbridge/via/vt8237r/nic.c | 62 +++ src/southbridge/via/vt8237r/pirq.c | 51 ++ src/southbridge/via/vt8237r/sata.c | 132 +++++ src/southbridge/via/vt8237r/usb.c | 165 ++++++ src/southbridge/via/vt8237r/vt8237_ctrl.c | 289 ---------- src/southbridge/via/vt8237r/vt8237_fadt.c | 173 ------ src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 498 ----------------- src/southbridge/via/vt8237r/vt8237r_ide.c | 132 ----- src/southbridge/via/vt8237r/vt8237r_lpc.c | 624 ---------------------- src/southbridge/via/vt8237r/vt8237r_nic.c | 62 --- src/southbridge/via/vt8237r/vt8237r_pirq.c | 51 -- src/southbridge/via/vt8237r/vt8237r_sata.c | 132 ----- src/southbridge/via/vt8237r/vt8237r_usb.c | 165 ------ 19 files changed, 2133 insertions(+), 2133 deletions(-) create mode 100644 src/southbridge/via/vt8237r/ctrl.c create mode 100644 src/southbridge/via/vt8237r/early_smbus.c create mode 100644 src/southbridge/via/vt8237r/fadt.c create mode 100644 src/southbridge/via/vt8237r/ide.c create mode 100644 src/southbridge/via/vt8237r/lpc.c create mode 100644 src/southbridge/via/vt8237r/nic.c create mode 100644 src/southbridge/via/vt8237r/pirq.c create mode 100644 src/southbridge/via/vt8237r/sata.c create mode 100644 src/southbridge/via/vt8237r/usb.c delete mode 100644 src/southbridge/via/vt8237r/vt8237_ctrl.c delete mode 100644 src/southbridge/via/vt8237r/vt8237_fadt.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_early_smbus.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_ide.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_lpc.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_nic.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_pirq.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_sata.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_usb.c (limited to 'src/southbridge/via/vt8237r') diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index 04adb4b6d9..dd14a00fdc 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -18,10 +18,10 @@ ## driver-y += vt8237r.c -driver-y += vt8237_ctrl.c -driver-y += vt8237r_ide.c -driver-y += vt8237r_lpc.c -driver-y += vt8237r_sata.c -driver-y += vt8237r_usb.c -driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c +driver-y += ctrl.c +driver-y += ide.c +driver-y += lpc.c +driver-y += sata.c +driver-y += usb.c +driver-$(CONFIG_PIRQ_ROUTE) += pirq.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c new file mode 100644 index 0000000000..f3cc30ed88 --- /dev/null +++ b/src/southbridge/via/vt8237r/ctrl.c @@ -0,0 +1,289 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "vt8237r.h" + +/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */ + +static void vt8237_cfg(struct device *dev) +{ + u8 regm, regm3; + device_t devfun3; + + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_3, 0); + if (!devfun3) + die("Unknown NB"); + + /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */ + pci_write_config8(dev, 0x70, 0xc2); + pci_write_config8(dev, 0x71, 0xc8); + + /* PCI Control */ + pci_write_config8(dev, 0x72, 0xee); + pci_write_config8(dev, 0x73, 0x01); + pci_write_config8(dev, 0x74, 0x3c); + pci_write_config8(dev, 0x75, 0x0f); + pci_write_config8(dev, 0x76, 0x50); + pci_write_config8(dev, 0x77, 0x48); + pci_write_config8(dev, 0x78, 0x01); + /* APIC on HT */ + /* Maybe Enable LDT APIC Mode bit3 set to 1 */ + pci_write_config8(dev, 0x7c, 0x77); + + /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ + + regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x57, regm); + + regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ + pci_write_config8(dev, 0x61, regm); + + regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ + pci_write_config8(dev, 0x62, regm); + + /* Shadow page F + memhole copy */ + regm = pci_read_config8(devfun3, 0x83); + pci_write_config8(dev, 0x63, regm); + + // FIXME is this really supposed to be regm3? + regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + pci_write_config8(dev, 0x64, regm); + + regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ + pci_write_config8(dev, 0xe6, regm); +} + +/** + * Example of setup: Setup the V-Link for VT8237R, 8X mode. + * + * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: + * + * REG DEF AW VIA-8X VIA-4X + * ----------------------------- + * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 + * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 + * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 + * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 + * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 + * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 + * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 + * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 + * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 + * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 + */ + +/* we setup 533MB/s mode full duplex */ + +static void vt8237s_vlink_init(struct device *dev) +{ + u8 reg; + device_t devfun7; + + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_7, 0); + /* No pairing NB was found. */ + if (!devfun7) + return; + + /* + * This init code is valid only for the VT8237S! For different + * sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R) + * and VT8251) a different init code is required. + */ + + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ + pci_write_config8(devfun7, 0xb5, 0x66); + pci_write_config8(devfun7, 0xb6, 0x66); + pci_write_config8(devfun7, 0xb7, 0x64); + + reg = pci_read_config8(devfun7, 0xb4); + reg |= 0x1; + reg &= ~0x10; + pci_write_config8(devfun7, 0xb4, reg); + + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x60); + pci_write_config8(dev, 0xb9, 0x88); + pci_write_config8(dev, 0xba, 0x88); + pci_write_config8(dev, 0xbb, 0x89); + + reg = pci_read_config8(dev, 0xbd); + reg |= 0x3; + reg &= ~0x4; + pci_write_config8(dev, 0xbd, reg); + + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + /* Program V-link 8X 8bit full duplex, parity enabled. */ + pci_write_config8(dev, 0x48, 0x23 | 0x80); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); + +} + +static void vt8237a_vlink_init(struct device *dev) +{ + u8 reg; + device_t devfun7; + + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_7, 0); + /* No pairing NB was found. */ + if (!devfun7) + return; + + /* + * This init code is valid only for the VT8237A! For different + * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different + * init code is required. + * + * FIXME: This is based on vt8237r_vlink_init() in + * k8t890/k8t890_ctrl.c and modified to fit what the AMI + * BIOS on my M2V wrote to these registers (by looking + * at lspci -nxxx output). + * Works for me. + */ + + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ + pci_write_config8(devfun7, 0xb5, 0x88); + pci_write_config8(devfun7, 0xb6, 0x88); + pci_write_config8(devfun7, 0xb7, 0x61); + + reg = pci_read_config8(devfun7, 0xb4); + reg |= 0x11; + pci_write_config8(devfun7, 0xb4, reg); + + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x50); + pci_write_config8(dev, 0xb9, 0x88); + pci_write_config8(dev, 0xba, 0x8a); + pci_write_config8(dev, 0xbb, 0x88); + + reg = pci_read_config8(dev, 0xbd); + reg |= 0x3; + reg &= ~0x4; + pci_write_config8(dev, 0xbd, reg); + + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + pci_write_config8(dev, 0x48, 0x23); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); +} + +static void ctrl_enable(struct device *dev) +{ + /* Enable the 0:13 and 0:13.1. */ + /* FIXME */ + pci_write_config8(dev, 0x4f, 0x43); +} + +static void ctrl_init(struct device *dev) +{ + /* + * TODO: Fix some ordering issue for V-link set Rx77[6] and + * PCI1_Rx4F[0] should to 1. + * FIXME DO you need? + */ + + /* + * VT8237R specific configuration. Other SB are done in their own + * directories. TODO: Add A version. + */ + device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + if (devsb) { + vt8237s_vlink_init(dev); + } + + devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (devsb) { + vt8237a_vlink_init(dev); + } + + /* Configure PCI1 and copy mirror registers from D0F3. */ + vt8237_cfg(dev); + dump_south(dev); +} + +static const struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ctrl_init, + .enable = ctrl_enable, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237_VLINK, +}; diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c new file mode 100644 index 0000000000..a298e84676 --- /dev/null +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -0,0 +1,498 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include "vt8237r.h" + +/** + * Print an error, should it occur. If no error, just exit. + * + * @param host_status The data returned on the host status register after + * a transaction is processed. + * @param loops The number of times a transaction was attempted. + */ +static void smbus_print_error(u8 host_status, int loops) +{ + /* Check if there actually was an error. */ + if ((host_status == 0x00 || host_status == 0x40 || + host_status == 0x42) && (loops < SMBUS_TIMEOUT)) + return; + + if (loops >= SMBUS_TIMEOUT) + print_err("SMBus timeout\n"); + if (host_status & (1 << 4)) + print_err("Interrupt/SMI# was Failed Bus Transaction\n"); + if (host_status & (1 << 3)) + print_err("Bus error\n"); + if (host_status & (1 << 2)) + print_err("Device error\n"); + if (host_status & (1 << 1)) + print_debug("Interrupt/SMI# completed successfully\n"); + if (host_status & (1 << 0)) + print_err("Host busy\n"); +} + +/** + * Wait for the SMBus to become ready to process the next transaction. + */ +static void smbus_wait_until_ready(void) +{ + int loops; + + PRINT_DEBUG("Waiting until SMBus ready\n"); + + /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the + * SMBus Host Status register to go to 0, indicating the operation + * was completed successfully. I don't remember why I did it this way, + * but I think it was because ROMCC was running low on registers */ + loops = 0; + while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) + ++loops; + + smbus_print_error(inb(SMBHSTSTAT), loops); +} + +/** + * Reset and take ownership of the SMBus. + */ +static void smbus_reset(void) +{ + outb(HOST_RESET, SMBHSTSTAT); + + /* Datasheet says we have to read it to take ownership of SMBus. */ + inb(SMBHSTSTAT); + + PRINT_DEBUG("After reset status: "); + PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); + PRINT_DEBUG("\n"); +} + +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u8 dimm, u8 offset) +{ + u8 val; + + PRINT_DEBUG("DIMM "); + PRINT_DEBUG_HEX16(dimm); + PRINT_DEBUG(" OFFSET "); + PRINT_DEBUG_HEX16(offset); + PRINT_DEBUG("\n"); + + smbus_reset(); + + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + PRINT_DEBUG("Read: "); + PRINT_DEBUG_HEX16(val); + PRINT_DEBUG("\n"); + + /* Probably don't have to do this, but it can't hurt. */ + smbus_reset(); + + return val; +} + +#define PSONREADY_TIMEOUT 0x7fffffff + +static device_t get_vt8237_lpc(void) +{ + device_t dev; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev != PCI_DEV_INVALID) + return dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + if (dev != PCI_DEV_INVALID) + return dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + return dev; +} + +/** + * Enable the SMBus on VT8237R-based systems. + */ +void enable_smbus(void) +{ + device_t dev; + int loops; + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); + + /* Make sure the RTC power well is up before touching smbus. */ + loops = 0; + while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) + && loops < PSONREADY_TIMEOUT) + ++loops; + + /* + * 7 = SMBus Clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp + */ + pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); + + /* Enable SMBus. */ + pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, + VT8237R_SMBUS_IO_BASE | 0x1); + + /* SMBus Host Configuration, enable. */ + pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); + + /* Make it work for I/O. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + smbus_reset(); + + /* Reset the internal pointer. */ + inb(SMBHSTCTL); +} + +/** + * A fixup for some systems that need time for the SMBus to "warm up". This is + * needed on some VT823x based systems, where the SMBus spurts out bad data for + * a short time after power on. This has been seen on the VIA Epia series and + * Jetway J7F2-series. It reads the ID byte from SMBus, looking for + * known-good data from a slot/address. Exits on either good data or a timeout. + * + * TODO: This should probably go into some global file, but one would need to + * be created just for it. If some other chip needs/wants it, we can + * worry about it then. + * + * @param ctrl The memory controller and SMBus addresses. + */ +void smbus_fixup(const struct mem_controller *ctrl) +{ + int i, ram_slots, current_slot = 0; + u8 result = 0; + + ram_slots = ARRAY_SIZE(ctrl->channel0); + if (!ram_slots) { + print_err("smbus_fixup() thinks there are no RAM slots!\n"); + return; + } + + PRINT_DEBUG("Waiting for SMBus to warm up"); + + /* + * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for + * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). + * VT8237R has only been seen on DDR and DDR2 based systems, so far. + */ + for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || + (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { + + if (current_slot > ram_slots) + current_slot = 0; + + result = smbus_read_byte(ctrl->channel0[current_slot], + SPD_MEMORY_TYPE); + current_slot++; + PRINT_DEBUG("."); + } + + if (i >= SMBUS_TIMEOUT) + print_err("SMBus timed out while warming up\n"); + else + PRINT_DEBUG("Done\n"); +} + +/* FIXME: Better separate the NB and SB, will be done once it works. */ + +void vt8237_sb_enable_fid_vid(void) +{ + device_t dev, devctl; + u16 devid; + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + return; + + devid = pci_read_config16(dev, PCI_DEVICE_ID); + + /* generic setup */ + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* chipset-specific parts */ + + /* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */ + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || + devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { + devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); + + if (devctl != PCI_DEV_INVALID) { + /* So the chip knows we are on AMD. */ + pci_write_config8(devctl, 0x7c, 0x7f); + } + } + + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + + outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + return; + } + + /* VT8237R and VT8237A */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); +} + +void enable_rom_decode(void) +{ + device_t dev; + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + return; + + /* ROM decode last 1MB FFC00000 - FFFFFFFF. */ + pci_write_config8(dev, 0x41, 0x7f); +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 +static int acpi_is_wakeup_early(void) { + device_t dev; + u16 tmp; + + print_debug("IN TEST WAKEUP\n"); + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + + print_debug_hex8(tmp); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} +#endif + +#if defined(__GNUC__) +void vt8237_early_spi_init(void) +{ + device_t dev; + volatile u16 *spireg; + u32 tmp; + + /* Bus Control and Power Management */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + + if (dev == PCI_DEV_INVALID) + die("SB not found\n"); + + /* Put SPI base 20 d0 fe. */ + tmp = pci_read_config32(dev, 0xbc); + pci_write_config32(dev, 0xbc, + (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); + + /* Set SPI clock to 33MHz. */ + spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); + (*spireg) &= 0xff00; +} +#endif + +/* This #if is special. ROMCC chokes on the (rom == NULL) comparison. + * Since the whole function is only called for one target and that target + * is compiled with GCC, hide the function from ROMCC and be happy. + */ +#if defined(__GNUC__) +/* + * Offset 0x58: + * 31:20 reserved + * 19:16 4 bit position in shadow EEPROM + * 15:0 data to write + * + * Offset 0x5c: + * 31:28 reserved + * 27 ERDBG - enable read from 0x5c + * 26 reserved + * 25 SEELD + * 24 SEEPR - write 1 when done updating, wait until SEELD is + * set to 1, sticky + * cleared by reset, if it is 1 writing is disabled + * 19:16 4 bit position in shadow EEPROM + * 15:0 data from shadow EEPROM + * + * After PCIRESET SEELD and SEEPR must be 1 and 1. + */ + +/* 1 = needs PCI reset, 0 don't reset, network initialized. */ + +/* FIXME: Maybe close the debug register after use? */ + +#define LAN_TIMEOUT 0x7FFFFFFF + +int vt8237_early_network_init(struct vt8237_network_rom *rom) +{ + struct vt8237_network_rom n; + int i, loops; + device_t dev; + u32 tmp; + u8 status; + u16 *rom_write; + unsigned int checksum; + + /* Network adapter */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8233_7), 0); + if (dev == PCI_DEV_INVALID) { + print_err("Network is disabled, please enable\n"); + return 0; + } + + tmp = pci_read_config32(dev, 0x5c); + tmp |= 0x08000000; /* Enable ERDBG. */ + pci_write_config32(dev, 0x5c, tmp); + + status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3); + + /* Network controller OK, EEPROM loaded. */ + if (status == 3) + return 0; + + if (rom == NULL) { + print_err("No config data specified, using default MAC!\n"); + n.mac_address[0] = 0x0; + n.mac_address[1] = 0x0; + n.mac_address[2] = 0xde; + n.mac_address[3] = 0xad; + n.mac_address[4] = 0xbe; + n.mac_address[5] = 0xef; + n.phy_addr = 0x1; + n.res1 = 0x0; + n.sub_sid = 0x102; + n.sub_vid = 0x1106; + n.pid = 0x3065; + n.vid = 0x1106; + n.pmcc = 0x1f; + n.data_sel = 0x10; + n.pmu_data_reg = 0x0; + n.aux_curr = 0x0; + n.reserved = 0x0; + n.min_gnt = 0x3; + n.max_lat = 0x8; + n.bcr0 = 0x9; + n.bcr1 = 0xe; + n.cfg_a = 0x3; + n.cfg_b = 0x0; + n.cfg_c = 0x40; + n.cfg_d = 0x82; + n.checksum = 0x0; + rom = &n; + } + + rom_write = (u16 *) rom; + checksum = 0; + /* Write all data except checksum and second to last byte. */ + tmp &= 0xff000000; /* Leave reserved bits in. */ + for (i = 0; i < 15; i++) { + pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); + /* Lame code FIXME */ + checksum += rom_write[i] & 0xff; + /* checksum %= 256; */ + checksum += (rom_write[i] >> 8) & 0xff; + /* checksum %= 256; */ + } + + checksum += (rom_write[15] & 0xff); + checksum = ~(checksum & 0xff); + tmp |= (((checksum & 0xff) << 8) | rom_write[15]); + + /* Write last byte and checksum. */ + pci_write_config32(dev, 0x58, (15 << 16) | tmp); + + tmp = pci_read_config32(dev, 0x5c); + pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */ + + /* Yes, this is a mess, but it's the easiest way to do it. */ + /* XXX not so messy, but an explanation of the hack would have been better */ + loops = 0; + while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) + && (loops < LAN_TIMEOUT)) { + ++loops; + } + + if (loops >= LAN_TIMEOUT) { + print_err("Timeout - LAN controller didn't accept config\n"); + return 0; + } + + /* We are done, config will be used after PCIRST#. */ + return 1; +} +#endif diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c new file mode 100644 index 0000000000..6976f4d447 --- /dev/null +++ b/src/southbridge/via/vt8237r/fadt.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007, 2009 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "vt8237r.h" + +/** + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + device_t dev; + int is_vt8237s = 0; + + /* Power management controller */ + dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + + if (dev) + is_vt8237s = 1; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 4; + memcpy(header->oem_id, "COREBO", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 42; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4; + fadt->pm1b_cnt_blk = 0x0; + /* once we support C2/C3 this could be set to 0x22 and chipset needs to be adjusted too */ + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8; + fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20; + if (is_vt8237s) { + fadt->gpe1_blk = VT8237R_ACPI_IO_BASE + 0x60; + fadt->gpe1_base = 0x10; + fadt->gpe1_blk_len = 4; + } else { + fadt->gpe1_blk = 0x0; + fadt->gpe1_base = 0; + fadt->gpe1_blk_len = 0; + } + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 90; + fadt->p_lvl3_lat = 900; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 1; //?? + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ + fadt->iapc_boot_arch = 0xb; + /* check me */ + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c new file mode 100644 index 0000000000..209437b729 --- /dev/null +++ b/src/southbridge/via/vt8237r/ide.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on other VIA SB code. */ + +#include +#include +#include +#include +#include "vt8237r.h" +#include "chip.h" + +/** + * Cable type detect function, weak so it can be overloaded in mainboard.c + */ +u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev) +{ + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *)dev->chip_info; + u32 res; + res = sb->ide0_80pin_cable ? VT8237R_IDE0_80PIN_CABLE : 0; + res |= sb->ide1_80pin_cable ? VT8237R_IDE1_80PIN_CABLE : 0; + return res; +} + +/** + * No native mode. Interrupts from unconnected HDDs might occur if + * IRQ14/15 is used for PCI. Therefore no native mode support. + */ +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *)dev->chip_info; + + u8 enables; + u32 cablesel; + + printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", + sb->ide0_enable ? "enabled" : "disabled"); + printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", + sb->ide1_enable ? "enabled" : "disabled"); + enables = pci_read_config8(dev, IDE_CS) & ~0x3; + enables |= (sb->ide0_enable << 1) | sb->ide1_enable; + pci_write_config8(dev, IDE_CS, enables); + enables = pci_read_config8(dev, IDE_CS); + printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); + + /* Enable only compatibility mode. */ + enables = pci_read_config8(dev, 0x09); + enables &= 0xFA; + pci_write_config8(dev, 0x09, enables); + + enables = pci_read_config8(dev, IDE_CONF_II); + enables &= ~0xc0; + pci_write_config8(dev, IDE_CONF_II, enables); + enables = pci_read_config8(dev, IDE_CONF_II); + printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); + + /* Enable prefetch buffers. */ + enables = pci_read_config8(dev, IDE_CONF_I); + enables |= 0xf0; + pci_write_config8(dev, IDE_CONF_I, enables); + + /* Flush FIFOs at half. */ + enables = pci_read_config8(dev, IDE_CONF_FIFO); + enables &= 0xf0; + enables |= (1 << 2) | (1 << 0); + pci_write_config8(dev, IDE_CONF_FIFO, enables); + + /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ + enables = pci_read_config8(dev, IDE_MISC_I); + enables &= 0xe2; + enables |= (1 << 4) | (1 << 3); + pci_write_config8(dev, IDE_MISC_I, enables); + + /* Use memory read multiple, Memory-Write-and-Invalidate. */ + enables = pci_read_config8(dev, IDE_MISC_II); + enables &= 0xEF; + enables |= (1 << 2) | (1 << 3); + pci_write_config8(dev, IDE_MISC_II, enables); + + /* Force interrupts to use compat mode. */ + pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Cable guy... */ + cablesel = pci_read_config32(dev, IDE_UDMA); + cablesel &= ~VT8237R_IDE_CABLESEL_MASK; + cablesel |= vt8237_ide_80pin_detect(dev); + pci_write_config32(dev, IDE_UDMA, cablesel); + +#if CONFIG_EPIA_VT8237R_INIT + device_t lpc_dev; + + /* Set PATA Output Drive Strength */ + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (lpc_dev) + pci_write_config8(lpc_dev, 0x7C, 0x20); +#endif +} + +static const struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c new file mode 100644 index 0000000000..72b85b37d5 --- /dev/null +++ b/src/southbridge/via/vt8237r/lpc.c @@ -0,0 +1,624 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * Copyright (C) 2009 Jon Harrison + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Inspiration from other VIA SB code. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vt8237r.h" +#include "chip.h" + +static void southbridge_init_common(struct device *dev); + +#if CONFIG_EPIA_VT8237R_INIT + /* Interrupts for INT# A B C D */ +static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; + + /* Interrupt Assignments for Pins 1 2 3 4 */ +static const unsigned char sataPins[4] = { 'A','B','C','D'}; +static const unsigned char vgaPins[4] = { 'A','B','C','D'}; +static const unsigned char usbPins[4] = { 'A','B','C','D'}; +static const unsigned char enetPins[4] = { 'A','B','C','D'}; +static const unsigned char vt8237Pins[4] = { 'A','B','C','D'}; +static const unsigned char slotPins[4] = { 'C','D','A','B'}; +static const unsigned char riserPins[4] = { 'D','C','B','A'}; + +static unsigned char *pin_to_irq(const unsigned char *pin) +{ + static unsigned char Irqs[4]; + int i; + for (i = 0 ; i < 4 ; i++) + Irqs[i] = pciIrqs[ pin[i] - 'A' ]; + + return Irqs; +} +#endif + +/** Set up PCI IRQ routing, route everything through APIC. */ +static void pci_routing_fixup(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + device_t pdev; +#endif + + /* PCI PNP Interrupt Routing INTE/F - disable */ + pci_write_config8(dev, 0x44, 0x00); + + /* PCI PNP Interrupt Routing INTG/H - disable */ + pci_write_config8(dev, 0x45, 0x00); + + /* Gate Interrupts until RAM Writes are flushed */ + pci_write_config8(dev, 0x49, 0x20); + +#if CONFIG_EPIA_VT8237R_INIT + + /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ + pci_write_config8(dev, 0x46, 0x00); + + /* setup PCI IRQ routing (For PCI Slot)*/ + pci_write_config8(dev, 0x55, pciIrqs[0] << 4); + pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); + pci_write_config8(dev, 0x57, pciIrqs[3] << 4); + + /* PCI Routing Fixup */ + + //Setup MiniPCI Slot + pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); + + // Via 2 slot riser card 2nd slot + pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); + + //Setup USB + pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); + + //Setup VT8237R Sound + pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins)); + + //Setup Ethernet + pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); + + //Setup VGA + pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); + + /* APIC Routing Fixup */ + + // Setup SATA + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT6420_SATA, 0); + pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02); + pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins)); + + + // Setup PATA Override + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_82C586_1, 0); + pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01); + pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); + +#else + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + + /* PCI Interrupt Polarity */ + pci_write_config8(dev, 0x54, 0x00); + + /* PCI INTA# Routing */ + pci_write_config8(dev, 0x55, 0x00); + + /* PCI INTB#/C# Routing */ + pci_write_config8(dev, 0x56, 0x00); + + /* PCI INTD# Routing */ + pci_write_config8(dev, 0x57, 0x00); +#endif +} + + + +/** + * Set up the power management capabilities directly into ACPI mode. + * This avoids having to handle any System Management Interrupts (SMIs). + */ + +extern u8 acpi_slp_type; + + +static void setup_pm(device_t dev) +{ + u16 tmp; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ + pci_write_config8(dev, 0x80, 0x20); + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ + pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); + +#if CONFIG_EPIA_VT8237R_INIT + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x3052); +#else + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x30b2); + +#endif + /* SMI output level to low, 7.5us throttle clock */ + pci_write_config8(dev, 0x8d, 0x18); + + /* GP Timer Control 1s */ + pci_write_config8(dev, 0x93, 0x88); + + /* + * 7 = SMBus clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp disabled + * 2 = GPO2 is SUSA# + */ + pci_write_config8(dev, 0x94, 0xa0); + + /* + * 7 = stp to sust delay 1msec + * 6 = SUSST# Deasserted Before PWRGD for STD + * 5 = Keyboard/Mouse Swap + * 4 = PWRGOOD reset on VT8237A/S + * 3 = GPO26/GPO27 is GPO + * 2 = Disable Alert on Lan + * 1 = SUSCLK/GPO4 + * 0 = USB Wakeup + */ + +#if CONFIG_EPIA_VT8237R_INIT + pci_write_config8(dev, 0x95, 0xc2); +#else + pci_write_config8(dev, 0x95, 0xcc); +#endif + + /* Disable GP3 timer. */ + pci_write_config8(dev, 0x98, 0); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* Clear status events. */ + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00); + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20); + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28); + outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30); + + /* Disable SCI on GPIO. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x22); + + /* Disable SMI on GPIO. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x24); + + /* Disable all global enable SMIs. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x2a); + + /* All SMI off, both IDE buses ON, PSON rising edge. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x2c); + + /* Primary activity SMI disable. */ + outl(0x0, VT8237R_ACPI_IO_BASE + 0x34); + + /* GP timer reload on none. */ + outl(0x0, VT8237R_ACPI_IO_BASE + 0x38); + + /* Disable extended IO traps. */ + outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); + + /* SCI is generated for RTC/pwrBtn/slpBtn. */ + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); +#endif + /* clear sleep */ + tmp &= ~(7 << 10); + tmp |= 1; + outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); +} + +static void vt8237r_init(struct device *dev) +{ + u8 enables; + +#if CONFIG_EPIA_VT8237R_INIT + printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); + /* + * TODO: Looks like stock BIOS can do this but causes a hang + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + * Setup to match EPIA default + * PCS0# on Pin U1 + */ + enables = pci_read_config8(dev, 0xe5); + enables |= 0x23; + pci_write_config8(dev, 0xe5, enables); + + /* + * Enable Flash Write Access. + * Note EPIA-N Does not use REQ5 or PCISTP#(Hang) + */ + enables = pci_read_config8(dev, 0xe4); + enables |= 0x2B; + pci_write_config8(dev, 0xe4, enables); + + /* Enables Extra RTC Ports */ + enables = pci_read_config8(dev, 0x4E); + enables |= 0x80; + pci_write_config8(dev, 0x4E, enables); + +#else + printk(BIOS_SPEW, "Entering vt8237r_init.\n"); + /* + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x09); + + /* REQ5 as PCI request input - should be together with INTE-INTH. */ + pci_write_config8(dev, 0xe4, 0x4); +#endif + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + +#if CONFIG_EPIA_VT8237R_INIT + /* + * Set Read Pass Write Control Enable + */ + pci_write_config8(dev, 0x48, 0x0c); +#else + /* + * Set Read Pass Write Control Enable + * (force A2 from APIC FSB to low). + */ + pci_write_config8(dev, 0x48, 0x8c); +#endif + + southbridge_init_common(dev); + +#if !CONFIG_EPIA_VT8237R_INIT + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); +#endif + + printk(BIOS_SPEW, "Leaving %s.\n", __func__); +} + +static void vt8237a_init(struct device *dev) +{ + /* + * FIXME: This is based on vt8237s_init() and the values the AMI + * BIOS on my M2V wrote to these registers (by loking + * at lspci -nxxx output). + * Works for me. + */ + u32 tmp; + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + tmp = pci_read_config8(dev, 0x4f); + tmp |= 0x08; + pci_write_config8(dev, 0x4f, tmp); + + /* + * bit2: REQ5 as PCI request input - should be together with INTE-INTH. + * bit5: usb power control lines as gpio + */ + pci_write_config8(dev, 0xe4, 0x24); + /* + * Enable APIC wakeup from INTH + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x69); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at VT8237R_HPET_ADDR. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + southbridge_init_common(dev); + + /* Share INTE-INTH with INTA-INTD for simplicity */ + pci_write_config8(dev, 0x46, 0x00); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); + + dump_south(dev); +} + +static void vt8237s_init(struct device *dev) +{ + u32 tmp; + + /* Put SPI base VT8237S_SPI_MEM_BASE. */ + tmp = pci_read_config32(dev, 0xbc); + pci_write_config32(dev, 0xbc, + (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); + + /* + * REQ5 as PCI request input - should be together with INTE-INTH. + */ + pci_write_config8(dev, 0xe4, 0x04); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + southbridge_init_common(dev); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2. + */ + outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); + + dump_south(dev); +} + +static void vt8237_common_init(struct device *dev) +{ + u8 enables, byte; + + /* Enable addr/data stepping. */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte |= PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); + +/* EPIA-N(L) Uses CN400 for BIOS Access */ +#if !CONFIG_EPIA_VT8237R_INIT + /* Enable the internal I/O decode. */ + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + /* + * ROM decode + * bit range + * 7 000E0000h-000EFFFFh + * 6 FFF00000h-FFF7FFFFh + * 5 FFE80000h-FFEFFFFFh + * 4 FFE00000h-FFE7FFFFh + * 3 FFD80000h-FFDFFFFFh + * 2 FFD00000h-FFD7FFFFh + * 1 FFC80000h-FFCFFFFFh + * 0 FFC00000h-FFC7FFFFh + * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. + */ + pci_write_config8(dev, 0x41, 0x7f); +#endif + + /* + * Set bit 6 of 0x40 (I/O recovery time). + * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so + * that PCI interrupts can be properly marked as level triggered. + */ + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + /* Line buffer control */ + enables = pci_read_config8(dev, 0x42); + enables |= 0xf8; + pci_write_config8(dev, 0x42, enables); + + /* Delay transaction control */ + pci_write_config8(dev, 0x43, 0xb); + +#if CONFIG_EPIA_VT8237R_INIT + /* I/O recovery time, default IDE routing */ + pci_write_config8(dev, 0x4c, 0x04); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* + * Bit | Meaning + * ------------- + * 3 | Bypass APIC De-Assert Message (1=Enable) + * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * 0 | Dynamic Clock Gating Main Switch (1=Enable) + */ + pci_write_config8(dev, 0x5b, 0x9); + + /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/ + pci_write_config8(dev, 0x58, 0x42); + + /* Enable serial IRQ, 6PCI clocks. */ + pci_write_config8(dev, 0x52, 0x9); +#else + /* I/O recovery time, default IDE routing */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* + * Bit | Meaning + * ------------- + * 3 | Bypass APIC De-Assert Message (1=Enable) + * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * 0 | Dynamic Clock Gating Main Switch (1=Enable) + */ + pci_write_config8(dev, 0x5b, 0xb); + + /* Set 0x58 to 0x43 APIC and RTC. */ + pci_write_config8(dev, 0x58, 0x43); + + /* Enable serial IRQ, 6PCI clocks. */ + pci_write_config8(dev, 0x52, 0x9); + +#endif + + /* Power management setup */ + setup_pm(dev); + + /* Start the RTC. */ + rtc_init(0); +} + +static void vt8237r_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + /* Fixed ACPI Base IO Base*/ + res = new_resource(dev, 0x88); + res->base = VT8237R_ACPI_IO_BASE; + res->size = 128; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed EISA ECLR I/O Regs */ + res = new_resource(dev, 3); + res->base = 0x4d0; + res->size = 2; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed System Management Bus I/O Resource */ + res = new_resource(dev, 0xD0); + res->base = VT8237R_SMBUS_IO_BASE; + res->size = 16; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed APIC resource */ + res = new_resource(dev, 0x44); + res->base = IO_APIC_ADDR; + res->size = 256; + res->limit = 0xffffffffUL; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed flashrom resource */ + res = new_resource(dev, 4); + res->base = 0xff000000UL; + res->size = 0x01000000UL; /* 16MB */ + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void init_keyboard(struct device *dev) +{ + u8 regval = pci_read_config8(dev, 0x51); + if (regval & 0x1) + pc_keyboard_init(0); +} + +static void southbridge_init_common(struct device *dev) +{ + vt8237_common_init(dev); + pci_routing_fixup(dev); + setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID); + setup_i8259(); + init_keyboard(dev); +} + +static const struct device_operations vt8237r_lpc_ops_s = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237s_init, + .scan_bus = scan_static_bus, +}; + +static const struct device_operations vt8237r_lpc_ops_r = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237r_init, + .scan_bus = scan_static_bus, +}; + +static const struct device_operations vt8237r_lpc_ops_a = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237a_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver_r __pci_driver = { + .ops = &vt8237r_lpc_ops_r, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, +}; + +static const struct pci_driver lpc_driver_a __pci_driver = { + .ops = &vt8237r_lpc_ops_a, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, +}; + +static const struct pci_driver lpc_driver_s __pci_driver = { + .ops = &vt8237r_lpc_ops_s, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237S_LPC, +}; diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c new file mode 100644 index 0000000000..6771895916 --- /dev/null +++ b/src/southbridge/via/vt8237r/nic.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * Copyright (C) 2009 Jon Harrison + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "vt8237r.h" + + +static void vt8237_eth_read_resources(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + struct resource *res; + + /* Fix the I/O Resources of the USB2.0 Interface */ + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = 0xF6001000ULL; + res->size = 256; + res->align = 12; + res->gran = 8; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED; +#else + pci_dev_read_resources(dev); +#endif + return; +} + + +static const struct device_operations vt8237_eth_ops = { + .read_resources = vt8237_eth_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver vt8237r_driver_eth __pci_driver = { + .ops = &vt8237_eth_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8233_7, +}; diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c new file mode 100644 index 0000000000..9915da4835 --- /dev/null +++ b/src/southbridge/via/vt8237r/pirq.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov + * Copyright (C) 2010 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +void pirq_assign_irqs(const unsigned char route[4]) +{ + device_t pdev; + + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (!pdev) + return; + + pci_write_config8(pdev, 0x55, route[0] << 4); + pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); + pci_write_config8(pdev, 0x57, route[3] << 4); + + /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ + pci_write_config8(pdev, 0x46, 0x00); +} +#endif diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c new file mode 100644 index 0000000000..777d605a6b --- /dev/null +++ b/src/southbridge/via/vt8237r/sata.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +#define SATA_MISC_CTRL 0x45 + +static void sata_i_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); + + /* Class IDE Disk */ + reg = pci_read_config8(dev, SATA_MISC_CTRL); + reg &= 0x7f; /* Sub Class Write Protect off */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); + + /* Change the device class to SATA from RAID. */ + pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); + reg |= 0x80; /* Sub Class Write Protect on */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); + + return; +} + +static void sata_ii_init(struct device *dev) +{ + u8 reg; + + sata_i_init(dev); + + /* + * Analog black magic, you may or may not need to adjust 0x60-0x6f, + * depends on PCB. + */ + + /* + * Analog PHY - gen1 + * CDR bandwidth [6:5] = 3 + * Squelch Window Select [4:3] = 1 + * CDR Charge Pump [2:0] = 1 + */ + + pci_write_config8(dev, 0x64, 0x49); + + /* Adjust driver current source value to 9. */ + reg = pci_read_config8(dev, 0x65); + reg &= 0xf0; + reg |= 0x9; + pci_write_config8(dev, 0x65, reg); + + /* Set all manual termination 50ohm bits [2:0] and enable [4]. */ + reg = pci_read_config8(dev, 0x6a); + reg |= 0xf; + pci_write_config8(dev, 0x6a, reg); + + /* + * Analog PHY - gen2 + * CDR bandwidth [5:4] = 2 + * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e + * CDR Charge Pump [2:0] = 1 + */ + + reg = pci_read_config8(dev, 0x6f); + reg &= 0x08; + reg |= 0x61; + pci_write_config8(dev, 0x6f, reg); + + /* Check if staggered spinup is supported. */ + reg = pci_read_config8(dev, 0x83); + if ((reg & 0x8) == 0) { + /* Start OOB sequence on both drives. */ + reg |= 0x30; + pci_write_config8(dev, 0x83, reg); + } +} + +static const struct device_operations sata_i_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_i_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct device_operations sata_ii_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_ii_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_ii __pci_driver = { + .ops = &sata_ii_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237_SATA, +}; + +static const struct pci_driver northbridge_driver_i_a __pci_driver = { + .ops = &sata_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, +}; + +static const struct pci_driver northbridge_driver_i __pci_driver = { + .ops = &sata_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT6420_SATA, +}; diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c new file mode 100644 index 0000000000..6e8d9e5dd0 --- /dev/null +++ b/src/southbridge/via/vt8237r/usb.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * Copyright (C) 2009 Jon Harrison + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "vt8237r.h" + +#if CONFIG_EPIA_VT8237R_INIT +u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; +#endif + +static void usb_i_init(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + u8 reg8; + + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + reg8 = pci_read_config8(dev, 0x04); + + printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); + + reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, 0x04, reg8); + + printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); + + /* Set Cache Line Size and Latency Timer */ + pci_write_config8(dev, 0x0c, 0x08); + pci_write_config8(dev, 0x0d, 0x20); + + /* Enable Sub Device ID Back Door and set Generic */ + reg8 = pci_read_config8(dev, 0x42); + reg8 |= 0x10; + pci_write_config8(dev, 0x42, reg8); + pci_write_config16(dev, 0x2e, 0xAA07); + reg8 &= ~0x10; + pci_write_config8(dev, 0x42, reg8); + + + pci_write_config8(dev, 0x41, 0x12); + + pci_write_config8(dev, 0x49, 0x0B); + + /* Clear PCI Status */ + pci_write_config16(dev, 0x06, 0x7A10); +#endif + return; +} + +static void vt8237_usb_i_read_resources(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + struct resource *res; + u8 function = (u8) dev->path.pci.devfn & 0x7; + + printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); + + /* Fix the I/O Resources of the USB1.1 Interfaces */ + /* Auto PCI probe seems to size the resources */ + /* Incorrectly */ + res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = usb_io_addr[function]; + res->size = 256; + res->limit = 0xffffUL; + res->align = 10; + res->gran = 8; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED; +#else + pci_dev_read_resources(dev); +#endif + return; +} + +static void usb_ii_init(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + u8 reg8; + + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + /* Set memory Write and Invalidate */ + reg8 = pci_read_config8(dev, 0x04); + reg8 |= 0x10; + pci_write_config8(dev, 0x04, reg8); + + /* Set Cache line Size and Latency Timer */ + pci_write_config8(dev, 0x0c, 0x08); + pci_write_config8(dev, 0x0d, 0x20); + + /* Clear PCI Status */ + pci_write_config16(dev, 0x06, 0x7A10); +#endif + +} + +static void vt8237_usb_ii_read_resources(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + struct resource *res; + + /* Fix the I/O Resources of the USB2.0 Interface */ + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = 0xF6000000ULL; + res->size = 256; + res->align = 12; + res->gran = 8; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED; +#else + pci_dev_read_resources(dev); +#endif + return; +} + +static const struct device_operations usb_i_ops = { + .read_resources = vt8237_usb_i_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_i_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct device_operations usb_ii_ops = { + .read_resources = vt8237_usb_ii_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ii_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver vt8237r_driver_usbii __pci_driver = { + .ops = &usb_ii_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_EHCI, +}; + +static const struct pci_driver vt8237r_driver_usbi __pci_driver = { + .ops = &usb_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_UHCI, +}; diff --git a/src/southbridge/via/vt8237r/vt8237_ctrl.c b/src/southbridge/via/vt8237r/vt8237_ctrl.c deleted file mode 100644 index f3cc30ed88..0000000000 --- a/src/southbridge/via/vt8237r/vt8237_ctrl.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "vt8237r.h" - -/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */ - -static void vt8237_cfg(struct device *dev) -{ - u8 regm, regm3; - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - if (!devfun3) - die("Unknown NB"); - - /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */ - pci_write_config8(dev, 0x70, 0xc2); - pci_write_config8(dev, 0x71, 0xc8); - - /* PCI Control */ - pci_write_config8(dev, 0x72, 0xee); - pci_write_config8(dev, 0x73, 0x01); - pci_write_config8(dev, 0x74, 0x3c); - pci_write_config8(dev, 0x75, 0x0f); - pci_write_config8(dev, 0x76, 0x50); - pci_write_config8(dev, 0x77, 0x48); - pci_write_config8(dev, 0x78, 0x01); - /* APIC on HT */ - /* Maybe Enable LDT APIC Mode bit3 set to 1 */ - pci_write_config8(dev, 0x7c, 0x77); - - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); - - /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm); - - // FIXME is this really supposed to be regm3? - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ - pci_write_config8(dev, 0x64, regm); - - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); -} - -/** - * Example of setup: Setup the V-Link for VT8237R, 8X mode. - * - * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: - * - * REG DEF AW VIA-8X VIA-4X - * ----------------------------- - * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 - * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 - * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 - * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 - * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 - * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 - * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 - * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 - * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 - * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 - */ - -/* we setup 533MB/s mode full duplex */ - -static void vt8237s_vlink_init(struct device *dev) -{ - u8 reg; - device_t devfun7; - - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_7, 0); - /* No pairing NB was found. */ - if (!devfun7) - return; - - /* - * This init code is valid only for the VT8237S! For different - * sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R) - * and VT8251) a different init code is required. - */ - - /* disable auto disconnect */ - reg = pci_read_config8(devfun7, 0x42); - reg &= ~0x4; - pci_write_config8(devfun7, 0x42, reg); - - /* NB part setup */ - pci_write_config8(devfun7, 0xb5, 0x66); - pci_write_config8(devfun7, 0xb6, 0x66); - pci_write_config8(devfun7, 0xb7, 0x64); - - reg = pci_read_config8(devfun7, 0xb4); - reg |= 0x1; - reg &= ~0x10; - pci_write_config8(devfun7, 0xb4, reg); - - pci_write_config8(devfun7, 0xb0, 0x6); - pci_write_config8(devfun7, 0xb1, 0x1); - - /* SB part setup */ - pci_write_config8(dev, 0xb7, 0x60); - pci_write_config8(dev, 0xb9, 0x88); - pci_write_config8(dev, 0xba, 0x88); - pci_write_config8(dev, 0xbb, 0x89); - - reg = pci_read_config8(dev, 0xbd); - reg |= 0x3; - reg &= ~0x4; - pci_write_config8(dev, 0xbd, reg); - - reg = pci_read_config8(dev, 0xbc); - reg &= ~0x7; - pci_write_config8(dev, 0xbc, reg); - - /* Program V-link 8X 8bit full duplex, parity enabled. */ - pci_write_config8(dev, 0x48, 0x23 | 0x80); - - /* enable auto disconnect, for STPGNT and HALT */ - reg = pci_read_config8(devfun7, 0x42); - reg |= 0x7; - pci_write_config8(devfun7, 0x42, reg); - -} - -static void vt8237a_vlink_init(struct device *dev) -{ - u8 reg; - device_t devfun7; - - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_7, 0); - /* No pairing NB was found. */ - if (!devfun7) - return; - - /* - * This init code is valid only for the VT8237A! For different - * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different - * init code is required. - * - * FIXME: This is based on vt8237r_vlink_init() in - * k8t890/k8t890_ctrl.c and modified to fit what the AMI - * BIOS on my M2V wrote to these registers (by looking - * at lspci -nxxx output). - * Works for me. - */ - - /* disable auto disconnect */ - reg = pci_read_config8(devfun7, 0x42); - reg &= ~0x4; - pci_write_config8(devfun7, 0x42, reg); - - /* NB part setup */ - pci_write_config8(devfun7, 0xb5, 0x88); - pci_write_config8(devfun7, 0xb6, 0x88); - pci_write_config8(devfun7, 0xb7, 0x61); - - reg = pci_read_config8(devfun7, 0xb4); - reg |= 0x11; - pci_write_config8(devfun7, 0xb4, reg); - - pci_write_config8(devfun7, 0xb0, 0x6); - pci_write_config8(devfun7, 0xb1, 0x1); - - /* SB part setup */ - pci_write_config8(dev, 0xb7, 0x50); - pci_write_config8(dev, 0xb9, 0x88); - pci_write_config8(dev, 0xba, 0x8a); - pci_write_config8(dev, 0xbb, 0x88); - - reg = pci_read_config8(dev, 0xbd); - reg |= 0x3; - reg &= ~0x4; - pci_write_config8(dev, 0xbd, reg); - - reg = pci_read_config8(dev, 0xbc); - reg &= ~0x7; - pci_write_config8(dev, 0xbc, reg); - - pci_write_config8(dev, 0x48, 0x23); - - /* enable auto disconnect, for STPGNT and HALT */ - reg = pci_read_config8(devfun7, 0x42); - reg |= 0x7; - pci_write_config8(devfun7, 0x42, reg); -} - -static void ctrl_enable(struct device *dev) -{ - /* Enable the 0:13 and 0:13.1. */ - /* FIXME */ - pci_write_config8(dev, 0x4f, 0x43); -} - -static void ctrl_init(struct device *dev) -{ - /* - * TODO: Fix some ordering issue for V-link set Rx77[6] and - * PCI1_Rx4F[0] should to 1. - * FIXME DO you need? - */ - - /* - * VT8237R specific configuration. Other SB are done in their own - * directories. TODO: Add A version. - */ - device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - if (devsb) { - vt8237s_vlink_init(dev); - } - - devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); - if (devsb) { - vt8237a_vlink_init(dev); - } - - /* Configure PCI1 and copy mirror registers from D0F3. */ - vt8237_cfg(dev); - dump_south(dev); -} - -static const struct device_operations ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ctrl_init, - .enable = ctrl_enable, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237_VLINK, -}; diff --git a/src/southbridge/via/vt8237r/vt8237_fadt.c b/src/southbridge/via/vt8237r/vt8237_fadt.c deleted file mode 100644 index 6976f4d447..0000000000 --- a/src/southbridge/via/vt8237r/vt8237_fadt.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2009 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "vt8237r.h" - -/** - * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. - */ -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - device_t dev; - int is_vt8237s = 0; - - /* Power management controller */ - dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - - if (dev) - is_vt8237s = 1; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 4; - memcpy(header->oem_id, "COREBO", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 42; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - fadt->preferred_pm_profile = 0; - fadt->sci_int = 9; - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4; - fadt->pm1b_cnt_blk = 0x0; - /* once we support C2/C3 this could be set to 0x22 and chipset needs to be adjusted too */ - fadt->pm2_cnt_blk = 0x0; - fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8; - fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20; - if (is_vt8237s) { - fadt->gpe1_blk = VT8237R_ACPI_IO_BASE + 0x60; - fadt->gpe1_base = 0x10; - fadt->gpe1_blk_len = 4; - } else { - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - } - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 90; - fadt->p_lvl3_lat = 900; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 0; - fadt->duty_width = 1; //?? - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ - fadt->iapc_boot_arch = 0xb; - /* check me */ - fadt->flags = 0xa5; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c deleted file mode 100644 index a298e84676..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include "vt8237r.h" - -/** - * Print an error, should it occur. If no error, just exit. - * - * @param host_status The data returned on the host status register after - * a transaction is processed. - * @param loops The number of times a transaction was attempted. - */ -static void smbus_print_error(u8 host_status, int loops) -{ - /* Check if there actually was an error. */ - if ((host_status == 0x00 || host_status == 0x40 || - host_status == 0x42) && (loops < SMBUS_TIMEOUT)) - return; - - if (loops >= SMBUS_TIMEOUT) - print_err("SMBus timeout\n"); - if (host_status & (1 << 4)) - print_err("Interrupt/SMI# was Failed Bus Transaction\n"); - if (host_status & (1 << 3)) - print_err("Bus error\n"); - if (host_status & (1 << 2)) - print_err("Device error\n"); - if (host_status & (1 << 1)) - print_debug("Interrupt/SMI# completed successfully\n"); - if (host_status & (1 << 0)) - print_err("Host busy\n"); -} - -/** - * Wait for the SMBus to become ready to process the next transaction. - */ -static void smbus_wait_until_ready(void) -{ - int loops; - - PRINT_DEBUG("Waiting until SMBus ready\n"); - - /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the - * SMBus Host Status register to go to 0, indicating the operation - * was completed successfully. I don't remember why I did it this way, - * but I think it was because ROMCC was running low on registers */ - loops = 0; - while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) - ++loops; - - smbus_print_error(inb(SMBHSTSTAT), loops); -} - -/** - * Reset and take ownership of the SMBus. - */ -static void smbus_reset(void) -{ - outb(HOST_RESET, SMBHSTSTAT); - - /* Datasheet says we have to read it to take ownership of SMBus. */ - inb(SMBHSTSTAT); - - PRINT_DEBUG("After reset status: "); - PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); - PRINT_DEBUG("\n"); -} - -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) -{ - u8 val; - - PRINT_DEBUG("DIMM "); - PRINT_DEBUG_HEX16(dimm); - PRINT_DEBUG(" OFFSET "); - PRINT_DEBUG_HEX16(offset); - PRINT_DEBUG("\n"); - - smbus_reset(); - - /* Clear host data port. */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* Actual addr to reg format. */ - dimm = (dimm << 1); - dimm |= 1; - outb(dimm, SMBXMITADD); - outb(offset, SMBHSTCMD); - - /* Start transaction, byte data read. */ - outb(0x48, SMBHSTCTL); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - val = inb(SMBHSTDAT0); - PRINT_DEBUG("Read: "); - PRINT_DEBUG_HEX16(val); - PRINT_DEBUG("\n"); - - /* Probably don't have to do this, but it can't hurt. */ - smbus_reset(); - - return val; -} - -#define PSONREADY_TIMEOUT 0x7fffffff - -static device_t get_vt8237_lpc(void) -{ - device_t dev; - - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev != PCI_DEV_INVALID) - return dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev != PCI_DEV_INVALID) - return dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); - return dev; -} - -/** - * Enable the SMBus on VT8237R-based systems. - */ -void enable_smbus(void) -{ - device_t dev; - int loops; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Make sure the RTC power well is up before touching smbus. */ - loops = 0; - while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) - && loops < PSONREADY_TIMEOUT) - ++loops; - - /* - * 7 = SMBus Clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp - */ - pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); - - /* Enable SMBus. */ - pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, - VT8237R_SMBUS_IO_BASE | 0x1); - - /* SMBus Host Configuration, enable. */ - pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); - - /* Make it work for I/O. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - smbus_reset(); - - /* Reset the internal pointer. */ - inb(SMBHSTCTL); -} - -/** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for - * known-good data from a slot/address. Exits on either good data or a timeout. - * - * TODO: This should probably go into some global file, but one would need to - * be created just for it. If some other chip needs/wants it, we can - * worry about it then. - * - * @param ctrl The memory controller and SMBus addresses. - */ -void smbus_fixup(const struct mem_controller *ctrl) -{ - int i, ram_slots, current_slot = 0; - u8 result = 0; - - ram_slots = ARRAY_SIZE(ctrl->channel0); - if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\n"); - return; - } - - PRINT_DEBUG("Waiting for SMBus to warm up"); - - /* - * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for - * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). - * VT8237R has only been seen on DDR and DDR2 based systems, so far. - */ - for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || - (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { - - if (current_slot > ram_slots) - current_slot = 0; - - result = smbus_read_byte(ctrl->channel0[current_slot], - SPD_MEMORY_TYPE); - current_slot++; - PRINT_DEBUG("."); - } - - if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\n"); - else - PRINT_DEBUG("Done\n"); -} - -/* FIXME: Better separate the NB and SB, will be done once it works. */ - -void vt8237_sb_enable_fid_vid(void) -{ - device_t dev, devctl; - u16 devid; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - return; - - devid = pci_read_config16(dev, PCI_DEVICE_ID); - - /* generic setup */ - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - /* chipset-specific parts */ - - /* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */ - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || - devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { - devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); - - if (devctl != PCI_DEV_INVALID) { - /* So the chip knows we are on AMD. */ - pci_write_config8(devctl, 0x7c, 0x7f); - } - } - - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - return; - } - - /* VT8237R and VT8237A */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); -} - -void enable_rom_decode(void) -{ - device_t dev; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - return; - - /* ROM decode last 1MB FFC00000 - FFFFFFFF. */ - pci_write_config8(dev, 0x41, 0x7f); -} - -#if CONFIG_HAVE_ACPI_RESUME == 1 -static int acpi_is_wakeup_early(void) { - device_t dev; - u16 tmp; - - print_debug("IN TEST WAKEUP\n"); - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - - print_debug_hex8(tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; -} -#endif - -#if defined(__GNUC__) -void vt8237_early_spi_init(void) -{ - device_t dev; - volatile u16 *spireg; - u32 tmp; - - /* Bus Control and Power Management */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - - if (dev == PCI_DEV_INVALID) - die("SB not found\n"); - - /* Put SPI base 20 d0 fe. */ - tmp = pci_read_config32(dev, 0xbc); - pci_write_config32(dev, 0xbc, - (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - - /* Set SPI clock to 33MHz. */ - spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); - (*spireg) &= 0xff00; -} -#endif - -/* This #if is special. ROMCC chokes on the (rom == NULL) comparison. - * Since the whole function is only called for one target and that target - * is compiled with GCC, hide the function from ROMCC and be happy. - */ -#if defined(__GNUC__) -/* - * Offset 0x58: - * 31:20 reserved - * 19:16 4 bit position in shadow EEPROM - * 15:0 data to write - * - * Offset 0x5c: - * 31:28 reserved - * 27 ERDBG - enable read from 0x5c - * 26 reserved - * 25 SEELD - * 24 SEEPR - write 1 when done updating, wait until SEELD is - * set to 1, sticky - * cleared by reset, if it is 1 writing is disabled - * 19:16 4 bit position in shadow EEPROM - * 15:0 data from shadow EEPROM - * - * After PCIRESET SEELD and SEEPR must be 1 and 1. - */ - -/* 1 = needs PCI reset, 0 don't reset, network initialized. */ - -/* FIXME: Maybe close the debug register after use? */ - -#define LAN_TIMEOUT 0x7FFFFFFF - -int vt8237_early_network_init(struct vt8237_network_rom *rom) -{ - struct vt8237_network_rom n; - int i, loops; - device_t dev; - u32 tmp; - u8 status; - u16 *rom_write; - unsigned int checksum; - - /* Network adapter */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8233_7), 0); - if (dev == PCI_DEV_INVALID) { - print_err("Network is disabled, please enable\n"); - return 0; - } - - tmp = pci_read_config32(dev, 0x5c); - tmp |= 0x08000000; /* Enable ERDBG. */ - pci_write_config32(dev, 0x5c, tmp); - - status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3); - - /* Network controller OK, EEPROM loaded. */ - if (status == 3) - return 0; - - if (rom == NULL) { - print_err("No config data specified, using default MAC!\n"); - n.mac_address[0] = 0x0; - n.mac_address[1] = 0x0; - n.mac_address[2] = 0xde; - n.mac_address[3] = 0xad; - n.mac_address[4] = 0xbe; - n.mac_address[5] = 0xef; - n.phy_addr = 0x1; - n.res1 = 0x0; - n.sub_sid = 0x102; - n.sub_vid = 0x1106; - n.pid = 0x3065; - n.vid = 0x1106; - n.pmcc = 0x1f; - n.data_sel = 0x10; - n.pmu_data_reg = 0x0; - n.aux_curr = 0x0; - n.reserved = 0x0; - n.min_gnt = 0x3; - n.max_lat = 0x8; - n.bcr0 = 0x9; - n.bcr1 = 0xe; - n.cfg_a = 0x3; - n.cfg_b = 0x0; - n.cfg_c = 0x40; - n.cfg_d = 0x82; - n.checksum = 0x0; - rom = &n; - } - - rom_write = (u16 *) rom; - checksum = 0; - /* Write all data except checksum and second to last byte. */ - tmp &= 0xff000000; /* Leave reserved bits in. */ - for (i = 0; i < 15; i++) { - pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); - /* Lame code FIXME */ - checksum += rom_write[i] & 0xff; - /* checksum %= 256; */ - checksum += (rom_write[i] >> 8) & 0xff; - /* checksum %= 256; */ - } - - checksum += (rom_write[15] & 0xff); - checksum = ~(checksum & 0xff); - tmp |= (((checksum & 0xff) << 8) | rom_write[15]); - - /* Write last byte and checksum. */ - pci_write_config32(dev, 0x58, (15 << 16) | tmp); - - tmp = pci_read_config32(dev, 0x5c); - pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */ - - /* Yes, this is a mess, but it's the easiest way to do it. */ - /* XXX not so messy, but an explanation of the hack would have been better */ - loops = 0; - while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) - && (loops < LAN_TIMEOUT)) { - ++loops; - } - - if (loops >= LAN_TIMEOUT) { - print_err("Timeout - LAN controller didn't accept config\n"); - return 0; - } - - /* We are done, config will be used after PCIRST#. */ - return 1; -} -#endif diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c deleted file mode 100644 index 209437b729..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_ide.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Based on other VIA SB code. */ - -#include -#include -#include -#include -#include "vt8237r.h" -#include "chip.h" - -/** - * Cable type detect function, weak so it can be overloaded in mainboard.c - */ -u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev) -{ - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - u32 res; - res = sb->ide0_80pin_cable ? VT8237R_IDE0_80PIN_CABLE : 0; - res |= sb->ide1_80pin_cable ? VT8237R_IDE1_80PIN_CABLE : 0; - return res; -} - -/** - * No native mode. Interrupts from unconnected HDDs might occur if - * IRQ14/15 is used for PCI. Therefore no native mode support. - */ -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - - u8 enables; - u32 cablesel; - - printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", - sb->ide0_enable ? "enabled" : "disabled"); - printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", - sb->ide1_enable ? "enabled" : "disabled"); - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= (sb->ide0_enable << 1) | sb->ide1_enable; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, 0x09); - enables &= 0xFA; - pci_write_config8(dev, 0x09, enables); - - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables &= 0xEF; - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~VT8237R_IDE_CABLESEL_MASK; - cablesel |= vt8237_ide_80pin_detect(dev); - pci_write_config32(dev, IDE_UDMA, cablesel); - -#if CONFIG_EPIA_VT8237R_INIT - device_t lpc_dev; - - /* Set PATA Output Drive Strength */ - lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (lpc_dev) - pci_write_config8(lpc_dev, 0x7C, 0x20); -#endif -} - -static const struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c deleted file mode 100644 index 72b85b37d5..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ /dev/null @@ -1,624 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Jon Harrison - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Inspiration from other VIA SB code. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "vt8237r.h" -#include "chip.h" - -static void southbridge_init_common(struct device *dev); - -#if CONFIG_EPIA_VT8237R_INIT - /* Interrupts for INT# A B C D */ -static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; - - /* Interrupt Assignments for Pins 1 2 3 4 */ -static const unsigned char sataPins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char usbPins[4] = { 'A','B','C','D'}; -static const unsigned char enetPins[4] = { 'A','B','C','D'}; -static const unsigned char vt8237Pins[4] = { 'A','B','C','D'}; -static const unsigned char slotPins[4] = { 'C','D','A','B'}; -static const unsigned char riserPins[4] = { 'D','C','B','A'}; - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char Irqs[4]; - int i; - for (i = 0 ; i < 4 ; i++) - Irqs[i] = pciIrqs[ pin[i] - 'A' ]; - - return Irqs; -} -#endif - -/** Set up PCI IRQ routing, route everything through APIC. */ -static void pci_routing_fixup(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - device_t pdev; -#endif - - /* PCI PNP Interrupt Routing INTE/F - disable */ - pci_write_config8(dev, 0x44, 0x00); - - /* PCI PNP Interrupt Routing INTG/H - disable */ - pci_write_config8(dev, 0x45, 0x00); - - /* Gate Interrupts until RAM Writes are flushed */ - pci_write_config8(dev, 0x49, 0x20); - -#if CONFIG_EPIA_VT8237R_INIT - - /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ - pci_write_config8(dev, 0x46, 0x00); - - /* setup PCI IRQ routing (For PCI Slot)*/ - pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); - pci_write_config8(dev, 0x57, pciIrqs[3] << 4); - - /* PCI Routing Fixup */ - - //Setup MiniPCI Slot - pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); - - // Via 2 slot riser card 2nd slot - pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); - - //Setup USB - pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); - - //Setup VT8237R Sound - pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins)); - - //Setup Ethernet - pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); - - //Setup VGA - pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); - - /* APIC Routing Fixup */ - - // Setup SATA - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT6420_SATA, 0); - pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02); - pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins)); - - - // Setup PATA Override - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_1, 0); - pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01); - pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); - -#else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); - - /* PCI Interrupt Polarity */ - pci_write_config8(dev, 0x54, 0x00); - - /* PCI INTA# Routing */ - pci_write_config8(dev, 0x55, 0x00); - - /* PCI INTB#/C# Routing */ - pci_write_config8(dev, 0x56, 0x00); - - /* PCI INTD# Routing */ - pci_write_config8(dev, 0x57, 0x00); -#endif -} - - - -/** - * Set up the power management capabilities directly into ACPI mode. - * This avoids having to handle any System Management Interrupts (SMIs). - */ - -extern u8 acpi_slp_type; - - -static void setup_pm(device_t dev) -{ - u16 tmp; - /* Debounce LID and PWRBTN# Inputs for 16ms. */ - pci_write_config8(dev, 0x80, 0x20); - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ - pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); - -#if CONFIG_EPIA_VT8237R_INIT - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x3052); -#else - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x30b2); - -#endif - /* SMI output level to low, 7.5us throttle clock */ - pci_write_config8(dev, 0x8d, 0x18); - - /* GP Timer Control 1s */ - pci_write_config8(dev, 0x93, 0x88); - - /* - * 7 = SMBus clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp disabled - * 2 = GPO2 is SUSA# - */ - pci_write_config8(dev, 0x94, 0xa0); - - /* - * 7 = stp to sust delay 1msec - * 6 = SUSST# Deasserted Before PWRGD for STD - * 5 = Keyboard/Mouse Swap - * 4 = PWRGOOD reset on VT8237A/S - * 3 = GPO26/GPO27 is GPO - * 2 = Disable Alert on Lan - * 1 = SUSCLK/GPO4 - * 0 = USB Wakeup - */ - -#if CONFIG_EPIA_VT8237R_INIT - pci_write_config8(dev, 0x95, 0xc2); -#else - pci_write_config8(dev, 0x95, 0xcc); -#endif - - /* Disable GP3 timer. */ - pci_write_config8(dev, 0x98, 0); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - /* Clear status events. */ - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00); - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20); - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28); - outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30); - - /* Disable SCI on GPIO. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x22); - - /* Disable SMI on GPIO. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x24); - - /* Disable all global enable SMIs. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x2a); - - /* All SMI off, both IDE buses ON, PSON rising edge. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x2c); - - /* Primary activity SMI disable. */ - outl(0x0, VT8237R_ACPI_IO_BASE + 0x34); - - /* GP timer reload on none. */ - outl(0x0, VT8237R_ACPI_IO_BASE + 0x38); - - /* Disable extended IO traps. */ - outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); - - /* SCI is generated for RTC/pwrBtn/slpBtn. */ - tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME == 1 - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif - /* clear sleep */ - tmp &= ~(7 << 10); - tmp |= 1; - outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); -} - -static void vt8237r_init(struct device *dev) -{ - u8 enables; - -#if CONFIG_EPIA_VT8237R_INIT - printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); - /* - * TODO: Looks like stock BIOS can do this but causes a hang - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - * Setup to match EPIA default - * PCS0# on Pin U1 - */ - enables = pci_read_config8(dev, 0xe5); - enables |= 0x23; - pci_write_config8(dev, 0xe5, enables); - - /* - * Enable Flash Write Access. - * Note EPIA-N Does not use REQ5 or PCISTP#(Hang) - */ - enables = pci_read_config8(dev, 0xe4); - enables |= 0x2B; - pci_write_config8(dev, 0xe4, enables); - - /* Enables Extra RTC Ports */ - enables = pci_read_config8(dev, 0x4E); - enables |= 0x80; - pci_write_config8(dev, 0x4E, enables); - -#else - printk(BIOS_SPEW, "Entering vt8237r_init.\n"); - /* - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - */ - pci_write_config8(dev, 0xe5, 0x09); - - /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); -#endif - - /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - -#if CONFIG_EPIA_VT8237R_INIT - /* - * Set Read Pass Write Control Enable - */ - pci_write_config8(dev, 0x48, 0x0c); -#else - /* - * Set Read Pass Write Control Enable - * (force A2 from APIC FSB to low). - */ - pci_write_config8(dev, 0x48, 0x8c); -#endif - - southbridge_init_common(dev); - -#if !CONFIG_EPIA_VT8237R_INIT - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); -#endif - - printk(BIOS_SPEW, "Leaving %s.\n", __func__); -} - -static void vt8237a_init(struct device *dev) -{ - /* - * FIXME: This is based on vt8237s_init() and the values the AMI - * BIOS on my M2V wrote to these registers (by loking - * at lspci -nxxx output). - * Works for me. - */ - u32 tmp; - - /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ - tmp = pci_read_config8(dev, 0x4f); - tmp |= 0x08; - pci_write_config8(dev, 0x4f, tmp); - - /* - * bit2: REQ5 as PCI request input - should be together with INTE-INTH. - * bit5: usb power control lines as gpio - */ - pci_write_config8(dev, 0xe4, 0x24); - /* - * Enable APIC wakeup from INTH - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - */ - pci_write_config8(dev, 0xe5, 0x69); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - /* Host Bus Power Management Control, maybe not needed */ - pci_write_config8(dev, 0x8c, 0x5); - - /* Enable HPET at VT8237R_HPET_ADDR. */ - pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); - - southbridge_init_common(dev); - - /* Share INTE-INTH with INTA-INTD for simplicity */ - pci_write_config8(dev, 0x46, 0x00); - - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); - - dump_south(dev); -} - -static void vt8237s_init(struct device *dev) -{ - u32 tmp; - - /* Put SPI base VT8237S_SPI_MEM_BASE. */ - tmp = pci_read_config32(dev, 0xbc); - pci_write_config32(dev, 0xbc, - (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - - /* - * REQ5 as PCI request input - should be together with INTE-INTH. - */ - pci_write_config8(dev, 0xe4, 0x04); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - /* Host Bus Power Management Control, maybe not needed */ - pci_write_config8(dev, 0x8c, 0x5); - - /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */ - pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); - - southbridge_init_common(dev); - - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2. - */ - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - - dump_south(dev); -} - -static void vt8237_common_init(struct device *dev) -{ - u8 enables, byte; - - /* Enable addr/data stepping. */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte |= PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); - -/* EPIA-N(L) Uses CN400 for BIOS Access */ -#if !CONFIG_EPIA_VT8237R_INIT - /* Enable the internal I/O decode. */ - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - /* - * ROM decode - * bit range - * 7 000E0000h-000EFFFFh - * 6 FFF00000h-FFF7FFFFh - * 5 FFE80000h-FFEFFFFFh - * 4 FFE00000h-FFE7FFFFh - * 3 FFD80000h-FFDFFFFFh - * 2 FFD00000h-FFD7FFFFh - * 1 FFC80000h-FFCFFFFFh - * 0 FFC00000h-FFC7FFFFh - * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. - */ - pci_write_config8(dev, 0x41, 0x7f); -#endif - - /* - * Set bit 6 of 0x40 (I/O recovery time). - * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so - * that PCI interrupts can be properly marked as level triggered. - */ - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); - - /* Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf8; - pci_write_config8(dev, 0x42, enables); - - /* Delay transaction control */ - pci_write_config8(dev, 0x43, 0xb); - -#if CONFIG_EPIA_VT8237R_INIT - /* I/O recovery time, default IDE routing */ - pci_write_config8(dev, 0x4c, 0x04); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* - * Bit | Meaning - * ------------- - * 3 | Bypass APIC De-Assert Message (1=Enable) - * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch - * 0 | Dynamic Clock Gating Main Switch (1=Enable) - */ - pci_write_config8(dev, 0x5b, 0x9); - - /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/ - pci_write_config8(dev, 0x58, 0x42); - - /* Enable serial IRQ, 6PCI clocks. */ - pci_write_config8(dev, 0x52, 0x9); -#else - /* I/O recovery time, default IDE routing */ - pci_write_config8(dev, 0x4c, 0x44); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* - * Bit | Meaning - * ------------- - * 3 | Bypass APIC De-Assert Message (1=Enable) - * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch - * 0 | Dynamic Clock Gating Main Switch (1=Enable) - */ - pci_write_config8(dev, 0x5b, 0xb); - - /* Set 0x58 to 0x43 APIC and RTC. */ - pci_write_config8(dev, 0x58, 0x43); - - /* Enable serial IRQ, 6PCI clocks. */ - pci_write_config8(dev, 0x52, 0x9); - -#endif - - /* Power management setup */ - setup_pm(dev); - - /* Start the RTC. */ - rtc_init(0); -} - -static void vt8237r_read_resources(device_t dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Fixed ACPI Base IO Base*/ - res = new_resource(dev, 0x88); - res->base = VT8237R_ACPI_IO_BASE; - res->size = 128; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed EISA ECLR I/O Regs */ - res = new_resource(dev, 3); - res->base = 0x4d0; - res->size = 2; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed System Management Bus I/O Resource */ - res = new_resource(dev, 0xD0); - res->base = VT8237R_SMBUS_IO_BASE; - res->size = 16; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed APIC resource */ - res = new_resource(dev, 0x44); - res->base = IO_APIC_ADDR; - res->size = 256; - res->limit = 0xffffffffUL; - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed flashrom resource */ - res = new_resource(dev, 4); - res->base = 0xff000000UL; - res->size = 0x01000000UL; /* 16MB */ - res->limit = 0xffffffffUL; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void init_keyboard(struct device *dev) -{ - u8 regval = pci_read_config8(dev, 0x51); - if (regval & 0x1) - pc_keyboard_init(0); -} - -static void southbridge_init_common(struct device *dev) -{ - vt8237_common_init(dev); - pci_routing_fixup(dev); - setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID); - setup_i8259(); - init_keyboard(dev); -} - -static const struct device_operations vt8237r_lpc_ops_s = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237s_init, - .scan_bus = scan_static_bus, -}; - -static const struct device_operations vt8237r_lpc_ops_r = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237r_init, - .scan_bus = scan_static_bus, -}; - -static const struct device_operations vt8237r_lpc_ops_a = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237a_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver_r __pci_driver = { - .ops = &vt8237r_lpc_ops_r, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, -}; - -static const struct pci_driver lpc_driver_a __pci_driver = { - .ops = &vt8237r_lpc_ops_a, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, -}; - -static const struct pci_driver lpc_driver_s __pci_driver = { - .ops = &vt8237r_lpc_ops_s, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237S_LPC, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_nic.c b/src/southbridge/via/vt8237r/vt8237r_nic.c deleted file mode 100644 index 6771895916..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_nic.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Jon Harrison - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "vt8237r.h" - - -static void vt8237_eth_read_resources(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - struct resource *res; - - /* Fix the I/O Resources of the USB2.0 Interface */ - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = 0xF6001000ULL; - res->size = 256; - res->align = 12; - res->gran = 8; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - - -static const struct device_operations vt8237_eth_ops = { - .read_resources = vt8237_eth_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver vt8237r_driver_eth __pci_driver = { - .ops = &vt8237_eth_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_pirq.c b/src/southbridge/via/vt8237r/vt8237r_pirq.c deleted file mode 100644 index 9915da4835..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_pirq.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov - * Copyright (C) 2010 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) -void pirq_assign_irqs(const unsigned char route[4]) -{ - device_t pdev; - - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (!pdev) - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - if (!pdev) - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); - if (!pdev) - return; - - pci_write_config8(pdev, 0x55, route[0] << 4); - pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); - pci_write_config8(pdev, 0x57, route[3] << 4); - - /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ - pci_write_config8(pdev, 0x46, 0x00); -} -#endif diff --git a/src/southbridge/via/vt8237r/vt8237r_sata.c b/src/southbridge/via/vt8237r/vt8237r_sata.c deleted file mode 100644 index 777d605a6b..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_sata.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -#define SATA_MISC_CTRL 0x45 - -static void sata_i_init(struct device *dev) -{ - u8 reg; - - printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); - - /* Class IDE Disk */ - reg = pci_read_config8(dev, SATA_MISC_CTRL); - reg &= 0x7f; /* Sub Class Write Protect off */ - pci_write_config8(dev, SATA_MISC_CTRL, reg); - - /* Change the device class to SATA from RAID. */ - pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); - reg |= 0x80; /* Sub Class Write Protect on */ - pci_write_config8(dev, SATA_MISC_CTRL, reg); - - return; -} - -static void sata_ii_init(struct device *dev) -{ - u8 reg; - - sata_i_init(dev); - - /* - * Analog black magic, you may or may not need to adjust 0x60-0x6f, - * depends on PCB. - */ - - /* - * Analog PHY - gen1 - * CDR bandwidth [6:5] = 3 - * Squelch Window Select [4:3] = 1 - * CDR Charge Pump [2:0] = 1 - */ - - pci_write_config8(dev, 0x64, 0x49); - - /* Adjust driver current source value to 9. */ - reg = pci_read_config8(dev, 0x65); - reg &= 0xf0; - reg |= 0x9; - pci_write_config8(dev, 0x65, reg); - - /* Set all manual termination 50ohm bits [2:0] and enable [4]. */ - reg = pci_read_config8(dev, 0x6a); - reg |= 0xf; - pci_write_config8(dev, 0x6a, reg); - - /* - * Analog PHY - gen2 - * CDR bandwidth [5:4] = 2 - * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e - * CDR Charge Pump [2:0] = 1 - */ - - reg = pci_read_config8(dev, 0x6f); - reg &= 0x08; - reg |= 0x61; - pci_write_config8(dev, 0x6f, reg); - - /* Check if staggered spinup is supported. */ - reg = pci_read_config8(dev, 0x83); - if ((reg & 0x8) == 0) { - /* Start OOB sequence on both drives. */ - reg |= 0x30; - pci_write_config8(dev, 0x83, reg); - } -} - -static const struct device_operations sata_i_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_i_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct device_operations sata_ii_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_ii_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_ii __pci_driver = { - .ops = &sata_ii_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237_SATA, -}; - -static const struct pci_driver northbridge_driver_i_a __pci_driver = { - .ops = &sata_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, -}; - -static const struct pci_driver northbridge_driver_i __pci_driver = { - .ops = &sata_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT6420_SATA, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_usb.c b/src/southbridge/via/vt8237r/vt8237r_usb.c deleted file mode 100644 index 6e8d9e5dd0..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_usb.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Jon Harrison - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "vt8237r.h" - -#if CONFIG_EPIA_VT8237R_INIT -u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; -#endif - -static void usb_i_init(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - u8 reg8; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - reg8 = pci_read_config8(dev, 0x04); - - printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); - - reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, 0x04, reg8); - - printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); - - /* Set Cache Line Size and Latency Timer */ - pci_write_config8(dev, 0x0c, 0x08); - pci_write_config8(dev, 0x0d, 0x20); - - /* Enable Sub Device ID Back Door and set Generic */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= 0x10; - pci_write_config8(dev, 0x42, reg8); - pci_write_config16(dev, 0x2e, 0xAA07); - reg8 &= ~0x10; - pci_write_config8(dev, 0x42, reg8); - - - pci_write_config8(dev, 0x41, 0x12); - - pci_write_config8(dev, 0x49, 0x0B); - - /* Clear PCI Status */ - pci_write_config16(dev, 0x06, 0x7A10); -#endif - return; -} - -static void vt8237_usb_i_read_resources(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - struct resource *res; - u8 function = (u8) dev->path.pci.devfn & 0x7; - - printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); - - /* Fix the I/O Resources of the USB1.1 Interfaces */ - /* Auto PCI probe seems to size the resources */ - /* Incorrectly */ - res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = usb_io_addr[function]; - res->size = 256; - res->limit = 0xffffUL; - res->align = 10; - res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - -static void usb_ii_init(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - u8 reg8; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - /* Set memory Write and Invalidate */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= 0x10; - pci_write_config8(dev, 0x04, reg8); - - /* Set Cache line Size and Latency Timer */ - pci_write_config8(dev, 0x0c, 0x08); - pci_write_config8(dev, 0x0d, 0x20); - - /* Clear PCI Status */ - pci_write_config16(dev, 0x06, 0x7A10); -#endif - -} - -static void vt8237_usb_ii_read_resources(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - struct resource *res; - - /* Fix the I/O Resources of the USB2.0 Interface */ - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = 0xF6000000ULL; - res->size = 256; - res->align = 12; - res->gran = 8; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - -static const struct device_operations usb_i_ops = { - .read_resources = vt8237_usb_i_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_i_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct device_operations usb_ii_ops = { - .read_resources = vt8237_usb_ii_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_ii_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver vt8237r_driver_usbii __pci_driver = { - .ops = &usb_ii_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_EHCI, -}; - -static const struct pci_driver vt8237r_driver_usbi __pci_driver = { - .ops = &usb_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_UHCI, -}; -- cgit v1.2.3