From 08e0fb881093c977488de6e8d701dd69369123ec Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Mon, 22 Mar 2010 16:33:25 +0000 Subject: Fix all the format string warnings. Some other random warnings. Signed-off-by: Myles Watson Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/rs780/rs780_pcie.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c | 2 +- src/southbridge/intel/i3100/i3100_lpc.c | 2 +- src/southbridge/intel/i3100/i3100_reset.c | 1 + src/southbridge/intel/i82801ax/i82801ax_lpc.c | 8 ++++---- src/southbridge/intel/i82801ex/i82801ex_reset.c | 3 ++- src/southbridge/intel/i82870/p64h2_ioapic.c | 2 +- src/southbridge/nvidia/ck804/ck804_nic.c | 8 ++++---- src/southbridge/nvidia/mcp55/mcp55_aza.c | 2 +- src/southbridge/nvidia/mcp55/mcp55_lpc.c | 4 ++-- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/sis/sis966/sis966_aza.c | 4 ++-- src/southbridge/sis/sis966/sis966_early_smbus.c | 2 +- src/southbridge/sis/sis966/sis966_lpc.c | 2 +- src/southbridge/sis/sis966/sis966_nic.c | 4 ++-- src/southbridge/sis/sis966/sis966_usb2.c | 2 +- 16 files changed, 26 insertions(+), 24 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c index 186266b8f1..5cea2fd650 100644 --- a/src/southbridge/amd/rs780/rs780_pcie.c +++ b/src/southbridge/amd/rs780/rs780_pcie.c @@ -255,7 +255,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) u32 gfx_gpp_sb_sel; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev->path.pci.devfn, dev->path.pci.devfn, port); gfx_gpp_sb_sel = port >= 4 && port <= 8 ? PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index 481d68c74f..136c03a88b 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -86,7 +86,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC case 0x64: diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index 4612c916d2..d629e2f144 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -317,7 +317,7 @@ static void lpc_init(struct device *dev) if (!res) { return; } - *((u8 *)(res->base + 0x31ff)) |= (1 << 0); + *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0); // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode // (register 0x10/0x11) while the old code used int 1 (register 0x12) diff --git a/src/southbridge/intel/i3100/i3100_reset.c b/src/southbridge/intel/i3100/i3100_reset.c index 3ac52decb6..3f35f5fb83 100644 --- a/src/southbridge/intel/i3100/i3100_reset.c +++ b/src/southbridge/intel/i3100/i3100_reset.c @@ -19,6 +19,7 @@ */ #include +#include void hard_reset(void) { diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index 3f0323bd0e..8fccdf0983 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -74,7 +74,7 @@ typedef struct southbridge_intel_i82801ax_config config_t; * specific IRQ values in your mainboards Config.lb. */ -void i82801ax_enable_apic(struct device *dev) +static void i82801ax_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; @@ -108,7 +108,7 @@ void i82801ax_enable_apic(struct device *dev) *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } -void i82801ax_enable_serial_irqs(struct device *dev) +static void i82801ax_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, @@ -220,7 +220,7 @@ static void gpio_init(device_t dev, uint16_t ich_model) } } -void i82801ax_rtc_init(struct device *dev) +static void i82801ax_rtc_init(struct device *dev) { uint8_t reg8; uint32_t reg32; @@ -240,7 +240,7 @@ void i82801ax_rtc_init(struct device *dev) pci_write_config8(dev, RTC_CONF, 0x04); } -void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) +static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) { uint16_t reg16; int i; diff --git a/src/southbridge/intel/i82801ex/i82801ex_reset.c b/src/southbridge/intel/i82801ex/i82801ex_reset.c index a1d92a7cc1..9936892efe 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_reset.c +++ b/src/southbridge/intel/i82801ex/i82801ex_reset.c @@ -1,6 +1,7 @@ #include +#include -void i82801ex_hard_reset(void) +void hard_reset(void) { /* Try rebooting through port 0xcf9 */ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c index d90fede890..b2523ff436 100644 --- a/src/southbridge/intel/i82870/p64h2_ioapic.c +++ b/src/southbridge/intel/i82870/p64h2_ioapic.c @@ -62,7 +62,7 @@ static void p64h2_ioapic_init(device_t dev) pIndexRegister = (volatile uint32_t*) memoryBase; pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); - printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %x DataAddr = %x\n", + printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/ck804_nic.c index cb8015c16b..7678fb50fb 100644 --- a/src/southbridge/nvidia/ck804/ck804_nic.c +++ b/src/southbridge/nvidia/ck804/ck804_nic.c @@ -18,11 +18,11 @@ static void nic_init(struct device *dev) int eeprom_valid = 0; struct southbridge_nvidia_ck804_config *conf; static uint32_t nic_index = 0; - uint8_t *base; + unsigned long base; struct resource *res; res = find_resource(dev, 0x10); - base = (uint8_t*)(unsigned long)res->base; + base = (unsigned long)res->base; #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 @@ -76,8 +76,8 @@ static void nic_init(struct device *dev) if (!eeprom_valid) { unsigned long mac_pos; mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ - mac_l = read32((uint8_t*)mac_pos) + nic_index; - mac_h = read32((uint8_t*)mac_pos + 4); + mac_l = read32(mac_pos) + nic_index; + mac_h = read32(mac_pos + 4); } #if 1 /* Set that into NIC MMIO. */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c index cea0b49e8c..d4b0e8f2fb 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_aza.c +++ b/src/southbridge/nvidia/mcp55/mcp55_aza.c @@ -230,7 +230,7 @@ static void aza_init(struct device *dev) return; base =(uint8_t *) res->base; - printk(BIOS_DEBUG, "base = %08x\n", base); + printk(BIOS_DEBUG, "base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 869e8392e2..84612890e9 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -80,7 +80,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev,0x44, 0xfed00001); hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } static void lpc_init(device_t dev) @@ -224,7 +224,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 5d669e78ae..a9fcac6ab0 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -189,7 +189,7 @@ void rl5c476_set_resources(device_t dev) resource = find_resource(dev,1); if( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; - printk(BIOS_DEBUG, "%s 1 ==> %x\n", dev_path(dev), resource->base); + printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } } diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/sis966_aza.c index 013f5895c1..8e8f8e0055 100644 --- a/src/southbridge/sis/sis966/sis966_aza.c +++ b/src/southbridge/sis/sis966/sis966_aza.c @@ -117,7 +117,7 @@ static int codec_detect(uint8_t *base) return 0; } - printk(BIOS_DEBUG, "Codec ID = %lx\n", dword); + printk(BIOS_DEBUG, "Codec ID = %x\n", dword); dword=0x1; return dword; @@ -293,7 +293,7 @@ static void aza_init(struct device *dev) return; base =(uint8_t *) res->base; - printk(BIOS_DEBUG, "base = %08x\n", base); + printk(BIOS_DEBUG, "base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/sis966_early_smbus.c index 98b824f88a..0f40872a4d 100644 --- a/src/southbridge/sis/sis966/sis966_early_smbus.c +++ b/src/southbridge/sis/sis966/sis966_early_smbus.c @@ -484,7 +484,7 @@ void sis_init_stage2(void) printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); msr = rdmsr(0xC001001A); - printk(BIOS_DEBUG, "Memory Top Bound %lx\n",msr.lo ); + printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo ); temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; temp16=0x0001<<(temp16-1); diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index c23e628970..39f1996ff4 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -214,7 +214,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c index 62017360e7..25853b03a4 100644 --- a/src/southbridge/sis/sis966/sis966_nic.c +++ b/src/southbridge/sis/sis966/sis966_nic.c @@ -274,7 +274,7 @@ static void nic_init(struct device *dev) return; } base = res->base; - printk(BIOS_DEBUG, "NIC base address %lx\n",base); + printk(BIOS_DEBUG, "NIC base address %x\n",base); if(!(val=phy_detect(base,&PhyAddr))) { @@ -291,7 +291,7 @@ static void nic_init(struct device *dev) // if that is valid we will use that - printk(BIOS_DEBUG, "EEPROM contents %x \n",ReadEEprom( dev, base, 0LL)); + printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev, base, 0LL)); for(i=0;i<3;i++) { //status = smbus_read_byte(dev_eeprom, i); ulValue=ReadEEprom( dev, base, i+3L); diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/sis966_usb2.c index 437583d12f..c2e5b9950b 100644 --- a/src/southbridge/sis/sis966/sis966_usb2.c +++ b/src/southbridge/sis/sis966/sis966_usb2.c @@ -95,7 +95,7 @@ static void usb2_init(struct device *dev) return; base =(uint8_t *) res->base; - printk(BIOS_DEBUG, "base = %08x\n", base); + printk(BIOS_DEBUG, "base = %p\n", base); write32(base+0x20, 0x2); //----------------------------------------------------------- -- cgit v1.2.3