From 1d93b88af2de9dd3af45ebaffcac4344baaf3d40 Mon Sep 17 00:00:00 2001
From: Joel Kitching <kitching@google.com>
Date: Wed, 26 Sep 2018 17:58:14 +0800
Subject: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic

- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag
- implement vboot_platform_is_resuming on platforms missing it
- add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges

[ originally https://review.coreboot.org/c/coreboot/+/28750 ]

BUG=b:114018226
TEST=compile coreboot

Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
---
 src/southbridge/intel/common/pmbase.c  | 13 +++++++++++++
 src/southbridge/intel/common/pmutil.h  |  2 ++
 src/southbridge/intel/i82371eb/Kconfig |  1 +
 src/southbridge/intel/i82801jx/Kconfig |  1 +
 4 files changed, 17 insertions(+)

(limited to 'src/southbridge')

diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c
index 360b63d9e4..2de57d6da4 100644
--- a/src/southbridge/intel/common/pmbase.c
+++ b/src/southbridge/intel/common/pmbase.c
@@ -14,13 +14,16 @@
  */
 
 #include <stdint.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/early_variables.h>
 #include <assert.h>
+#include <security/vboot/vboot_common.h>
 
 #include "pmbase.h"
+#include "pmutil.h"
 
 /* LPC PM Base Address Register */
 #define PMBASE		0x40
@@ -91,3 +94,13 @@ u8 read_pmbase8(const u8 addr)
 
 	return inb(lpc_get_pmbase() + addr);
 }
+
+int vboot_platform_is_resuming(void)
+{
+	u16 reg16 = read_pmbase16(PM1_STS);
+
+	if (!(reg16 & WAK_STS))
+		return 0;
+
+	return acpi_sleep_from_pm1(reg16) == ACPI_S3;
+}
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 273e0f8e9d..26134d9fad 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -17,6 +17,8 @@
 #ifndef INTEL_COMMON_PMUTIL_H
 #define INTEL_COMMON_PMUTIL_H
 
+#include <cpu/x86/smm.h>
+
 #define D31F0_PMBASE		0x40
 #define D31F0_GEN_PMCON_3	0xa4
 #define D31F0_GPIO_ROUT		0xb8
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index f22c6e90fc..6552099ed9 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -1,4 +1,5 @@
 config SOUTHBRIDGE_INTEL_I82371EB
+	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	bool
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index e56d692fb3..4308e29510 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -28,6 +28,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select COMMON_FADT
+	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 
 if SOUTHBRIDGE_INTEL_I82801JX
 
-- 
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