From 207880cd1127acd6f5f0f2241d753aa6b1c39da0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 10 Dec 2013 09:03:17 +0200 Subject: Declare acpi_is_wakeup_early() only once MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/agesa/hudson/hudson.h | 2 -- src/southbridge/amd/cimx/sb800/sb_cimx.h | 2 -- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb700/sb700.h | 4 ---- src/southbridge/amd/sb800/early_setup.c | 3 ++- src/southbridge/via/vt8237r/early_smbus.c | 6 +++++- 6 files changed, 8 insertions(+), 11 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 50f1738b4e..f67af05cd0 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -70,8 +70,6 @@ void hudson_clk_output_48Mhz(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -int acpi_is_wakeup_early(void); - #else void hudson_enable(device_t dev); void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 6267e1c55a..cd8c42b6e6 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -32,8 +32,6 @@ void sb_Late_Post(void); void sb_Before_Pci_Restore_Init(void); void sb_After_Pci_Restore_Init(void); -int acpi_is_wakeup_early(void); - /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, * coreboot may need to set this even more earlier diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ddba1a8438..b7a5e7786a 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -21,13 +21,13 @@ #define _SB700_EARLY_SETUP_C_ #include +#include #include #include #include #include #include -#include #include #include "sb700.h" #include "smbus.h" diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index b70e395831..2cbfdc9381 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -75,10 +75,6 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev); #endif -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void); -#endif - int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 213cae96e7..ef0548c10d 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -21,6 +21,7 @@ #define _SB800_EARLY_SETUP_C_ #include +#include #include #include #include "sb800.h" @@ -666,7 +667,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) } #if CONFIG_HAVE_ACPI_RESUME -static int acpi_is_wakeup_early(void) +int acpi_is_wakeup_early(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index b41e1ad925..02235005e5 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if !defined(__ROMCC__) +#include +#endif #include #include #include @@ -328,7 +331,8 @@ void enable_rom_decode(void) } #if CONFIG_HAVE_ACPI_RESUME -static int acpi_is_wakeup_early(void) { +int acpi_is_wakeup_early(void) +{ device_t dev; u16 tmp; -- cgit v1.2.3