From 2dc63895eb9250137c216ced33fb63fc91e0402a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 28 Jun 2018 14:13:06 +0200 Subject: sb/intel/bd82x6x/finalize: Use new PMBASE API Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/27286 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/finalize.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 06010d7192..a08535e979 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -18,16 +18,13 @@ #include #include #include -#include "pch.h" +#include #include #include "chip.h" #include "pch.h" void intel_pch_finalize_smm(void) { - u16 tco1_cnt; - u16 pmbase; - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { /* Copy flash regions from FREG0-4 to PR0-4 @@ -72,10 +69,7 @@ void intel_pch_finalize_smm(void) pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* TCO_Lock */ - pmbase = smm_get_pmbase(); - tco1_cnt = inw(pmbase + TCO1_CNT); - tco1_cnt |= TCO_LOCK; - outw(tco1_cnt, pmbase + TCO1_CNT); + write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); -- cgit v1.2.3