From 64ed2b73451de4b655b3fdda0ff42825a165c317 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 31 Mar 2010 14:47:43 +0000 Subject: Drop \r\n and \n\r as both print_XXX and printk now do this internally. Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/amd8111_early_smbus.c | 4 +-- src/southbridge/amd/cs5535/cs5535_early_setup.c | 12 ++++---- src/southbridge/amd/cs5536/cs5536_early_setup.c | 12 ++++---- src/southbridge/amd/cs5536/cs5536_early_smbus.c | 2 +- src/southbridge/amd/sb600/sb600_early_setup.c | 6 ++-- src/southbridge/amd/sb700/sb700_early_setup.c | 8 +++--- .../broadcom/bcm5785/bcm5785_early_smbus.c | 4 +-- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785_sata.c | 4 +-- .../intel/esb6300/esb6300_early_smbus.c | 4 +-- src/southbridge/intel/i3100/i3100_early_smbus.c | 2 +- .../intel/i82371eb/i82371eb_early_smbus.c | 4 +-- src/southbridge/intel/i82371eb/i82371eb_smbus.h | 2 +- .../intel/i82801ax/i82801ax_early_smbus.c | 4 +-- src/southbridge/intel/i82801ax/i82801ax_smbus.h | 4 +-- src/southbridge/intel/i82801ax/i82801ax_watchdog.c | 2 +- .../intel/i82801bx/i82801bx_early_smbus.c | 4 +-- src/southbridge/intel/i82801bx/i82801bx_smbus.h | 4 +-- src/southbridge/intel/i82801bx/i82801bx_watchdog.c | 2 +- .../intel/i82801cx/i82801cx_early_smbus.c | 2 +- .../intel/i82801dx/i82801dx_early_smbus.c | 6 ++-- .../intel/i82801ex/i82801ex_early_smbus.c | 6 ++-- src/southbridge/intel/i82801ex/i82801ex_watchdog.c | 2 +- .../intel/i82801gx/i82801gx_early_smbus.c | 2 +- src/southbridge/intel/i82801gx/i82801gx_watchdog.c | 2 +- src/southbridge/nvidia/ck804/ck804_early_smbus.c | 4 +-- src/southbridge/nvidia/ck804/ck804_lpc.c | 2 +- src/southbridge/nvidia/ck804/ck804_sata.c | 8 +++--- .../nvidia/mcp55/mcp55_early_setup_car.c | 2 +- src/southbridge/nvidia/mcp55/mcp55_early_smbus.c | 4 +-- src/southbridge/sis/sis966/sis966_aza.c | 4 +-- src/southbridge/sis/sis966/sis966_ide.c | 4 +-- src/southbridge/sis/sis966/sis966_nic.c | 8 +++--- src/southbridge/sis/sis966/sis966_sata.c | 4 +-- src/southbridge/sis/sis966/sis966_usb.c | 4 +-- src/southbridge/sis/sis966/sis966_usb2.c | 4 +-- src/southbridge/via/vt8231/vt8231_early_serial.c | 2 +- src/southbridge/via/vt8231/vt8231_early_smbus.c | 20 +++++++------- src/southbridge/via/vt8235/vt8235_early_smbus.c | 18 ++++++------ src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 32 +++++++++++----------- .../via/vt82c686/vt82c686_early_serial.c | 2 +- 41 files changed, 114 insertions(+), 114 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index c8996784de..11aa6f750e 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -9,7 +9,7 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); @@ -23,7 +23,7 @@ static void enable_smbus(void) /* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); } static int smbus_recv_byte(unsigned device) diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c index c23426e086..583602c3dd 100644 --- a/src/southbridge/amd/cs5535/cs5535_early_setup.c +++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c @@ -164,19 +164,19 @@ static int cs5535_early_setup(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n\r"); + print_debug("reboot from BIOS reset\n"); return; } - print_debug("Setup idsel\r\n"); + print_debug("Setup idsel\n"); cs5535_setup_idsel(); - print_debug("Setup iobase\r\n"); + print_debug("Setup iobase\n"); cs5535_usb_swapsif(); cs5535_setup_iobase(); - print_debug("Setup gpio\r\n"); + print_debug("Setup gpio\n"); cs5535_setup_gpio(); - print_debug("Setup cis_mode\r\n"); + print_debug("Setup cis_mode\n"); cs5535_setup_cis_mode(); - print_debug("Setup smbus\r\n"); + print_debug("Setup smbus\n"); cs5535_enable_smbus(); dummy(); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c index 8a553f57e0..cd8bffa868 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_setup.c +++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c @@ -257,18 +257,18 @@ static void cs5536_early_setup(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - //print_debug("reboot from BIOS reset\n\r"); + //print_debug("reboot from BIOS reset\n"); return; } - //print_debug("Setup idsel\r\n"); + //print_debug("Setup idsel\n"); cs5536_setup_idsel(); - //print_debug("Setup iobase\r\n"); + //print_debug("Setup iobase\n"); cs5536_usb_swapsif(); cs5536_setup_iobase(); - //print_debug("Setup gpio\r\n"); + //print_debug("Setup gpio\n"); cs5536_setup_gpio(); - //print_debug("Setup smbus\r\n"); + //print_debug("Setup smbus\n"); cs5536_enable_smbus(); - //print_debug("Setup power button\r\n"); + //print_debug("Setup power button\n"); cs5536_setup_power_button(); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c index 298feeed9b..ce8e690567 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c +++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c @@ -199,7 +199,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base, print_debug_hex8(error); print_debug(" device:"); print_debug_hex8(device); - print_debug("\r\n"); + print_debug("\n"); /* stop, clean up the error, and leave */ smbus_stop_condition(smbus_io_base); outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c index b7581ec352..dd2ed69cd2 100644 --- a/src/southbridge/amd/sb600/sb600_early_setup.c +++ b/src/southbridge/amd/sb600/sb600_early_setup.c @@ -44,7 +44,7 @@ static u8 get_sb600_revision(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } return pci_read_config8(dev, 0x08); @@ -290,10 +290,10 @@ static void sb600_devices_por_init(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n", get_sb600_revision()); /* sbPorAtStartOfTblCfg */ diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index 3777bd6288..5d2fde2a4c 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -51,7 +51,7 @@ static u8 set_sb700_revision(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } rev_id = pci_read_config8(dev, 0x08); @@ -81,7 +81,7 @@ static u8 set_sb700_revision(void) } else if (rev_id == 0x3D) { rev = 0x15; } else - die("It is not SB700 or SB710\r\n"); + die("It is not SB700 or SB710\n"); return rev; } @@ -306,10 +306,10 @@ static void sb700_devices_por_init(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", set_sb700_revision()); /* sbPorAtStartOfTblCfg */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c index b6a2fe506e..64b8d07245 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c @@ -13,10 +13,10 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index 136c03a88b..462d9edf2d 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -86,7 +86,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC case 0x64: diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c index 7cd9c27f35..e82fa3ca8e 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c @@ -53,13 +53,13 @@ static void sata_init(struct device *dev) for(i=0; i<4; i++) { mmio = base + 0x100 * i; byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c index 503d573dea..ae7cfcd227 100644 --- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c +++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c @@ -6,7 +6,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); @@ -92,7 +92,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; } diff --git a/src/southbridge/intel/i3100/i3100_early_smbus.c b/src/southbridge/intel/i3100/i3100_early_smbus.c index b7edb9b68c..79825d153a 100644 --- a/src/southbridge/intel/i3100/i3100_early_smbus.c +++ b/src/southbridge/intel/i3100/i3100_early_smbus.c @@ -26,7 +26,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c index 689dfed1d1..ada781ec26 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c +++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c @@ -38,9 +38,9 @@ static void enable_smbus(void) PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\r\n"); + die("SMBus controller not found\n"); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); /* Set the SMBus I/O base. */ pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h index e1893c5cb1..a1ede98eb6 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h +++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h @@ -192,7 +192,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned #if 0 print_debug("Read fail "); print_debug_hex16(status_register); - print_debug("\r\n"); + print_debug("\n"); #endif return SMBUS_ERROR; } diff --git a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c index d80c29c159..14fa924bea 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c +++ b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c @@ -58,7 +58,7 @@ static void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) @@ -69,7 +69,7 @@ static inline int smbus_read_byte(unsigned device, unsigned address) static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - print_err("Unimplemented smbus_write_byte() called\r\n"); + print_err("Unimplemented smbus_write_byte() called\n"); return; } diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h index 7a7850835b..e4ec70bc5f 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_smbus.h +++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.h @@ -116,7 +116,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { #warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\r\n"); + print_err("Untested smbus_write_block called\n"); #if 0 unsigned char global_control_register; unsigned char global_status_register; @@ -177,7 +177,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; #endif } diff --git a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c index 6a3d4947e8..cd0c20d98e 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c +++ b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c @@ -51,5 +51,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); } diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c index b8ec9b7528..66935661dd 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c +++ b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c @@ -58,7 +58,7 @@ static void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) @@ -69,7 +69,7 @@ static inline int smbus_read_byte(unsigned device, unsigned address) static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - print_err("Unimplemented smbus_write_byte() called\r\n"); + print_err("Unimplemented smbus_write_byte() called\n"); return; } diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h index 7a7850835b..e4ec70bc5f 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -116,7 +116,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { #warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\r\n"); + print_err("Untested smbus_write_block called\n"); #if 0 unsigned char global_control_register; unsigned char global_status_register; @@ -177,7 +177,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; #endif } diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c index fb45f521c5..fcb08a1a0c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c +++ b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c @@ -50,5 +50,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); } diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c index 9c3480283c..02420ef75b 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c @@ -5,7 +5,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c index 30d197c461..b36f03e83d 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c @@ -42,7 +42,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ @@ -119,7 +119,7 @@ static int smbus_read_byte(unsigned device, unsigned address) unsigned char global_status_register; unsigned char byte; - /*print_err("smbus_read_byte\r\n"); */ + /*print_err("smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { print_err_hex8(-2); return -2; @@ -169,7 +169,7 @@ static int smbus_read_byte(unsigned device, unsigned address) /* print_err("smbus_read_byte: "); print_err_hex32(device); print_err(" ad "); print_err_hex32(address); - print_err("value "); print_err_hex8(byte); print_err("\r\n"); + print_err("value "); print_err_hex8(byte); print_err("\n"); */ return byte; } diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index c86bf23bb7..0ad5c74ee0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -6,7 +6,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); print_debug_hex32(pci_read_config32(dev, 0x20)); @@ -35,7 +35,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va return; } - print_debug("Unimplemented smbus_write_byte() called.\r\n"); + print_debug("Unimplemented smbus_write_byte() called.\n"); #if 0 /* setup transaction */ @@ -125,7 +125,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; } diff --git a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c index 205ea87d94..26f6644763 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c +++ b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c @@ -24,6 +24,6 @@ void watchdog_off(void) /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n"); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } diff --git a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c b/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c index 7c0d97d2c8..7d3c80e8a7 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c +++ b/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c @@ -49,7 +49,7 @@ static void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\r\n"); + print_debug("SMBus controller enabled.\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c index 436a9227cd..a26786d7d0 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c +++ b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c @@ -49,5 +49,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH7 watchdog disabled\n"); } diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c index 2bf6732e79..db641415ff 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c +++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.c @@ -12,9 +12,9 @@ static void enable_smbus(void) device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\r\n"); + die("SMBus controller not found\n"); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* Set SMBus I/O base. */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index d68a5b1077..3458738f9b 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -250,7 +250,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); + printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c index 8eed906ce8..2a29689ad6 100644 --- a/src/southbridge/nvidia/ck804/ck804_sata.c +++ b/src/southbridge/nvidia/ck804/ck804_sata.c @@ -51,7 +51,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) return; dword = *(base + 0); - printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); if (dword == 0x113) { loop = 200000; // 2 do { @@ -60,11 +60,11 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); } dword = *(base + 0x40); - printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); if (dword == 0x113) { loop = 200000; //2 do { @@ -73,7 +73,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); } } #endif diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c index cee5f25a24..6d776d38bd 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c @@ -412,7 +412,7 @@ static int mcp55_early_setup_x(void) } out: - print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n"); + print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n"); mcp55_early_set_port(mcp55_num, busn, devn, io_base); mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x); diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c index e27664aa18..83ea61965b 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c @@ -33,10 +33,10 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); #if 0 if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); #endif /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1); diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/sis966_aza.c index 8e8f8e0055..60c99706fe 100644 --- a/src/southbridge/sis/sis966/sis966_aza.c +++ b/src/southbridge/sis/sis966/sis966_aza.c @@ -277,14 +277,14 @@ static void aza_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/southbridge/sis/sis966/sis966_ide.c b/src/southbridge/sis/sis966/sis966_ide.c index 1ee583f889..c57be5ade7 100644 --- a/src/southbridge/sis/sis966/sis966_ide.c +++ b/src/southbridge/sis/sis966/sis966_ide.c @@ -156,14 +156,14 @@ print_debug("IDE_INIT:---------->\n"); for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("IDE_INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c index 25853b03a4..b9cbf7a1be 100644 --- a/src/southbridge/sis/sis966/sis966_nic.c +++ b/src/southbridge/sis/sis966/sis966_nic.c @@ -270,7 +270,7 @@ static void nic_init(struct device *dev) if(!res) { - printk(BIOS_DEBUG, "NIC Cannot find resource..\r\n"); + printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); return; } base = res->base; @@ -278,7 +278,7 @@ static void nic_init(struct device *dev) if(!(val=phy_detect(base,&PhyAddr))) { - printk(BIOS_DEBUG, "PHY detect fail !!!!\r\n"); + printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; } @@ -321,14 +321,14 @@ static void nic_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } diff --git a/src/southbridge/sis/sis966/sis966_sata.c b/src/southbridge/sis/sis966/sis966_sata.c index 7fcee82f29..57a2d8870f 100644 --- a/src/southbridge/sis/sis966/sis966_sata.c +++ b/src/southbridge/sis/sis966/sis966_sata.c @@ -156,14 +156,14 @@ for (i=0;i<10;i++){ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/southbridge/sis/sis966/sis966_usb.c b/src/southbridge/sis/sis966/sis966_usb.c index e9761ba786..d49f2aabb4 100644 --- a/src/southbridge/sis/sis966/sis966_usb.c +++ b/src/southbridge/sis/sis966/sis966_usb.c @@ -81,14 +81,14 @@ static void usb_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("USB 1.1 INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/sis966_usb2.c index c2e5b9950b..6cb9873070 100644 --- a/src/southbridge/sis/sis966/sis966_usb2.c +++ b/src/southbridge/sis/sis966/sis966_usb2.c @@ -108,14 +108,14 @@ static void usb2_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("USB 2.0 INIT:<----------\n"); diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c index 1bfffed7f5..1083eb67e6 100644 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -39,7 +39,7 @@ static void enable_vt8231_serial(void) if (dev == PCI_DEV_INVALID) { outb(7, 0x80); - die("Serial controller not found\r\n"); + die("Serial controller not found\n"); } /* first, you have to enable the superio and superio config. diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index dbb6e213ae..34a1a5c5d8 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -30,7 +30,7 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); @@ -47,9 +47,9 @@ static void enable_smbus(void) c |= 1; pci_write_config8(dev, 4, c); print_debug_hex8(c); - print_debug(" is the comm register\r\n"); + print_debug(" is the comm register\n"); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } @@ -117,7 +117,7 @@ void smbus_reset(void) smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\r\n"); + print_debug("\n"); } static void smbus_print_error(unsigned char host_status_register) @@ -125,21 +125,21 @@ static void smbus_print_error(unsigned char host_status_register) print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\r\n"); + print_err("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c index 8030f2f3df..9442b6e4d0 100644 --- a/src/southbridge/via/vt8235/vt8235_early_smbus.c +++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c @@ -36,7 +36,7 @@ static void enable_smbus(void) PCI_DEVICE_ID_VIA_8235), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE @@ -91,7 +91,7 @@ static int smbus_wait_until_ready(void) while((c & 1) == 1) { print_debug("c is "); print_debug_hex8(c); - print_debug("\r\n"); + print_debug("\n"); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); /* nop */ } @@ -110,7 +110,7 @@ void smbus_reset(void) smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\r\n"); + print_debug("\n"); } @@ -137,21 +137,21 @@ static void smbus_print_error(unsigned char host_status_register) print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\r\n"); + print_err("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index 17b32d529f..533cbe0c88 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -39,17 +39,17 @@ static void smbus_print_error(u8 host_status, int loops) return; if (loops >= SMBUS_TIMEOUT) - print_err("SMBus timeout\r\n"); + print_err("SMBus timeout\n"); if (host_status & (1 << 4)) - print_err("Interrupt/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrupt/SMI# was Failed Bus Transaction\n"); if (host_status & (1 << 3)) - print_err("Bus error\r\n"); + print_err("Bus error\n"); if (host_status & (1 << 2)) - print_err("Device error\r\n"); + print_err("Device error\n"); if (host_status & (1 << 1)) - print_debug("Interrupt/SMI# completed successfully\r\n"); + print_debug("Interrupt/SMI# completed successfully\n"); if (host_status & (1 << 0)) - print_err("Host busy\r\n"); + print_err("Host busy\n"); } /** @@ -59,7 +59,7 @@ static void smbus_wait_until_ready(void) { int loops; - PRINT_DEBUG("Waiting until SMBus ready\r\n"); + PRINT_DEBUG("Waiting until SMBus ready\n"); loops = 0; /* Yes, this is a mess, but it's the easiest way to do it. */ @@ -81,7 +81,7 @@ static void smbus_reset(void) PRINT_DEBUG("After reset status: "); PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } /** @@ -98,7 +98,7 @@ u8 smbus_read_byte(u8 dimm, u8 offset) PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); smbus_reset(); @@ -121,7 +121,7 @@ u8 smbus_read_byte(u8 dimm, u8 offset) val = inb(SMBHSTDAT0); PRINT_DEBUG("Read: "); PRINT_DEBUG_HEX16(val); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Probably don't have to do this, but it can't hurt. */ smbus_reset(); @@ -144,7 +144,7 @@ void enable_smbus(void) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); } /* @@ -189,7 +189,7 @@ void smbus_fixup(const struct mem_controller *ctrl) ram_slots = ARRAY_SIZE(ctrl->channel0); if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\r\n"); + print_err("smbus_fixup() thinks there are no RAM slots!\n"); return; } @@ -213,9 +213,9 @@ void smbus_fixup(const struct mem_controller *ctrl) } if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\r\n"); + print_err("SMBus timed out while warming up\n"); else - PRINT_DEBUG("Done\r\n"); + PRINT_DEBUG("Done\n"); } /* FIXME: Better separate the NB and SB, will be done once it works. */ @@ -310,7 +310,7 @@ int acpi_is_wakeup_early(void) { dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); } /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ @@ -337,7 +337,7 @@ void vt8237_early_spi_init(void) PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("SB not found\r\n"); + die("SB not found\n"); /* Put SPI base 20 d0 fe. */ tmp = pci_read_config32(dev, 0xbc); diff --git a/src/southbridge/via/vt82c686/vt82c686_early_serial.c b/src/southbridge/via/vt82c686/vt82c686_early_serial.c index e5aff02b8a..70c68aaaf5 100644 --- a/src/southbridge/via/vt82c686/vt82c686_early_serial.c +++ b/src/southbridge/via/vt82c686/vt82c686_early_serial.c @@ -65,7 +65,7 @@ static void vt82c686_enable_serial(device_t dev, unsigned iobase) if (sbdev == PCI_DEV_INVALID) { /* Serial output is not yet working at this point, but * die() emits the POST code 0xff and halts the CPU, too. */ - die("Southbridge not found.\r\n"); + die("Southbridge not found.\n"); } /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ -- cgit v1.2.3