From a0aea5669b2ee33f5db7abccf71ac6862e12c5c3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 3 Jul 2017 21:38:53 +0200 Subject: sb/intel/lynxpoint: Add whitespace around '<<' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1b2a16e8eb70819c72efd50f30a57f3687f31bb5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/20458 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Martin Roth --- src/southbridge/intel/lynxpoint/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 37cd94b662..513063edc4 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -371,7 +371,7 @@ static void lpt_lp_pm_init(struct device *dev) pci_write_config32(dev, 0xac, pci_read_config32(dev, 0xac) | (1 << 21)); - pch_iobp_update(0xED00015C, ~(1<<11), 0x00003700); + pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); pch_iobp_update(0xED000118, ~0UL, 0x00c00000); pch_iobp_update(0xED000120, ~0UL, 0x00240000); pch_iobp_update(0xCA000000, ~0UL, 0x00000009); @@ -466,7 +466,7 @@ static void enable_lp_clock_gating(device_t dev) /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) - RCBA32_OR(0x2614, (1<<26)); + RCBA32_OR(0x2614, (1 << 26)); RCBA32_OR(0x900, 0x0000031f); -- cgit v1.2.3