From a2d6a40480c97043e9126c0fbc9e1a79db22d408 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 22 Mar 2013 11:24:45 -0700 Subject: lynxpoint: Fix LP clock gating setup for LPC This bit offset is incorrect and should only be set based on another bit in a different register. Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/2973 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/lynxpoint/lpc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b01489fad..2864876a83 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -458,7 +458,10 @@ static void enable_lp_clock_gating(device_t dev) RCBA32_OR(0x900, 0x0000031f); reg32 = RCBA32(CG); - reg32 |= (1 << 31); // LPC Dynamic + if (RCBA32(0x3454) & (1 << 4)) + reg32 &= ~(1 << 29); // LPC Dynamic + else + reg32 |= (1 << 29); // LPC Dynamic reg32 |= (1 << 30); // LP LPC reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 27); // HPET Dynamic -- cgit v1.2.3