From c51dc44bf2b76ac47b83ee76bee3357ce4b173de Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 7 Apr 2010 01:44:04 +0000 Subject: "no warnings day" last round for today. still warnings - help appreciated. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/broadcom/bcm5785/bcm5785.c | 11 ++++---- .../broadcom/bcm5785/bcm5785_early_setup.c | 15 +++-------- src/southbridge/broadcom/bcm5785/bcm5785_ide.c | 7 +---- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c | 1 - src/southbridge/broadcom/bcm5785/bcm5785_reset.c | 1 + src/southbridge/broadcom/bcm5785/bcm5785_sata.c | 30 ++++++++-------------- .../broadcom/bcm5785/bcm5785_sb_pci_main.c | 4 +-- src/southbridge/ricoh/rl5c476/rl5c476.c | 8 +++--- src/southbridge/via/vt8235/vt8235.c | 6 ----- src/southbridge/via/vt8235/vt8235_lpc.c | 12 ++++----- src/southbridge/via/vt8235/vt8235_usb.c | 3 +-- src/southbridge/via/vt8237r/vt8237r_lpc.c | 1 - 12 files changed, 31 insertions(+), 68 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 7eb4e607c7..3ac28e59ca 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -12,8 +12,7 @@ void bcm5785_enable(device_t dev) { device_t sb_pci_main_dev; device_t bus_dev; - unsigned index; - unsigned reg_old, reg; + // unsigned index; /* See if we are on the behind the pcix bridge */ bus_dev = dev->bus->dev; @@ -23,18 +22,17 @@ void bcm5785_enable(device_t dev) unsigned devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn); -// index = ((dev->path.pci.devfn & ~7) >> 3) + 8; + // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) { unsigned devfn; devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); -// index = ((dev->path.pci.devfn & ~7) >> 3) + 8; + // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else { // same bus unsigned devfn; - uint32_t id; devfn = (dev->path.pci.devfn) & ~7; if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { if(dev->device == 0x0036) //PCI-X Bridge @@ -43,7 +41,7 @@ void bcm5785_enable(device_t dev) { devfn -= (1<<3); } } sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn); -// index = dev->path.pci.devfn & 7; + // index = dev->path.pci.devfn & 7; } if (!sb_pci_main_dev) { return; @@ -51,6 +49,7 @@ void bcm5785_enable(device_t dev) // get index now #if 0 + unsigned reg_old, reg; if (index < 16) { reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48); reg &= ~(1 << index); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c index 66b270cdff..25ad7baf32 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c @@ -6,8 +6,6 @@ static void bcm5785_enable_rom(void) { unsigned char byte; - uint32_t dword; - uint16_t word; device_t addr; /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ @@ -109,7 +107,7 @@ static void ldtstop_sb(void) } -static void hard_reset(void) +void hard_reset(void) { bcm5785_enable_wdt_port_cf9(); @@ -120,7 +118,7 @@ static void hard_reset(void) outb(0x0e, 0x0cf9); } -static void soft_reset(void) +void soft_reset(void) { bcm5785_enable_wdt_port_cf9(); @@ -164,7 +162,6 @@ static void bcm5785_enable_msg(void) static void bcm5785_early_setup(void) { uint8_t byte; - uint16_t word; uint32_t dword; device_t dev; @@ -181,13 +178,12 @@ static void bcm5785_early_setup(void) byte |= (1<<0); // SATA enable pci_write_config8(dev, 0x84, byte); -// wdt and cf9 for later in coreboot_ram to call hard_reset +// WDT and cf9 for later in coreboot_ram to call hard_reset bcm5785_enable_wdt_port_cf9(); bcm5785_enable_msg(); -#if 1 // IDE related //F0 byte = pci_read_config8(dev, 0x4e); @@ -207,9 +203,8 @@ static void bcm5785_early_setup(void) byte = pci_read_config8(dev, 0x49); byte |= 1; // enable second channel pci_write_config8(dev, 0x49, byte); -#endif -//F2 + //F2 dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); byte = pci_read_config8(dev, 0x40); @@ -218,7 +213,6 @@ static void bcm5785_early_setup(void) pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end -#if 1 // USB related pci_write_config8(dev, 0x90, 0x40); pci_write_config8(dev, 0x92, 0x06); @@ -227,5 +221,4 @@ static void bcm5785_early_setup(void) pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func pci_write_config8(dev, 0xb4, 0x40); -#endif } diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c b/src/southbridge/broadcom/bcm5785/bcm5785_ide.c index 82263e8ec5..90a41680f6 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_ide.c @@ -12,9 +12,6 @@ static void bcm5785_ide_read_resources(device_t dev) { - struct resource *res; - unsigned long index; - /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -26,9 +23,6 @@ static void bcm5785_ide_read_resources(device_t dev) static void ide_init(struct device *dev) { - uint16_t word; - - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -36,6 +30,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index 462d9edf2d..e76dd3a45a 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -70,7 +70,6 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) unsigned link; uint32_t reg; int i; - int var_num = 0; reg = pci_read_config8(dev, 0x44); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c b/src/southbridge/broadcom/bcm5785/bcm5785_reset.c index b6fc5926b3..6e05e93711 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_reset.c @@ -4,6 +4,7 @@ */ #include +#include #define PCI_DEV(BUS, DEV, FN) ( \ (((BUS) & 0xFFF) << 20) | \ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c index e82fa3ca8e..ec92ecf7e9 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c @@ -12,17 +12,13 @@ #include #include "bcm5785.h" - static void sata_init(struct device *dev) { - uint8_t byte; - uint8_t *base; - uint8_t *mmio; + u32 mmio; struct resource *res; - unsigned int mmio_base; - volatile unsigned int *mmio_reg; + u32 mmio_base; int i; if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 @@ -31,27 +27,24 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0x78, byte); res = find_resource(dev, 0x24); - base = res->base; - - mmio_base = base; + mmio_base = res->base; mmio_base &= 0xfffffffc; - mmio_reg = (unsigned int *)( mmio_base + 0x10f0 ); - * mmio_reg = 0x40000001; - mmio_reg = ( unsigned int *)( mmio_base + 0x8c ); - * mmio_reg = 0x00ff2007; + + write32(mmio_base + 0x10f0, 0x40000001); + write32(mmio_base + 0x8c, 0x00ff2007); mdelay( 10 ); - * mmio_reg = 0x78592009; + write32(mmio_base + 0x8c, 0x78592009); mdelay( 10 ); - * mmio_reg = 0x00082004; + write32(mmio_base + 0x8c, 0x00082004); mdelay( 10 ); - * mmio_reg = 0x00002004; + write32(mmio_base + 0x8c, 0x00002004); mdelay( 10 ); //init PHY printk(BIOS_DEBUG, "init PHY...\n"); for(i=0; i<4; i++) { - mmio = base + 0x100 * i; + mmio = res->base + 0x100 * i; byte = read8(mmio + 0x40); printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set @@ -62,10 +55,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } - } - - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c index 69e077ebb0..a13e9f3fd0 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c @@ -25,8 +25,6 @@ static void sb_init(device_t dev) uint8_t byte_old; int nmi_option; - uint32_t dword; - /* Set up NMI on errors */ byte = inb(0x70); // RTC70 byte_old = byte; @@ -47,7 +45,6 @@ static void sb_init(device_t dev) static void bcm5785_sb_read_resources(device_t dev) { struct resource *res; - unsigned long index; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -64,6 +61,7 @@ static void bcm5785_sb_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } + static int lsmbus_recv_byte(device_t dev) { unsigned device; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index a9fcac6ab0..c276389bf7 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -162,7 +162,7 @@ static void rl5c476_init(device_t dev) *cptr = 0x41; } -void rl5c476_read_resources(device_t dev) +static void rl5c476_read_resources(device_t dev) { struct resource *resource; @@ -181,7 +181,7 @@ void rl5c476_read_resources(device_t dev) cardbus_read_resources(dev); } -void rl5c476_set_resources(device_t dev) +static void rl5c476_set_resources(device_t dev) { struct resource *resource; printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); @@ -212,12 +212,10 @@ static const struct pci_driver ricoh_rl5c476_driver __pci_driver = { .device = PCI_DEVICE_ID_RICOH_RL5C476, }; -void southbridge_init(device_t dev) +static void southbridge_init(device_t dev) { - struct southbridge_ricoh_rl5c476_config *conf = dev->chip_info; enable_cf_boot = conf->enable_cf; - } struct chip_operations southbridge_ricoh_rl5c476_ops = { diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c index 228da0f948..2687972afa 100644 --- a/src/southbridge/via/vt8235/vt8235.c +++ b/src/southbridge/via/vt8235/vt8235.c @@ -10,7 +10,6 @@ /* * Base VT8235. */ -static int enabled = 0; void hard_reset(void) { @@ -53,11 +52,9 @@ void set_led() static void vt8235_enable(struct device *dev) { - struct southbridge_via_vt8235_config *conf = dev->chip_info; unsigned char regval; unsigned short vendor,model; - vendor = pci_read_config16(dev,0); model = pci_read_config16(dev,0x2); @@ -72,7 +69,6 @@ static void vt8235_enable(struct device *dev) printk(BIOS_DEBUG, "Initialising Devices\n"); - setup_i8259(); // make sure interupt controller is configured before keyboard init /* enable RTC and ethernet */ @@ -87,8 +83,6 @@ static void vt8235_enable(struct device *dev) regval = pci_read_config8(dev, 0x50); regval &= ~(0x36); pci_write_config8(dev, 0x50, regval); - - } struct chip_operations southbridge_via_vt8235_ops = { diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c index 92ba973661..0746bc9a13 100644 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ b/src/southbridge/via/vt8235/vt8235_lpc.c @@ -105,9 +105,8 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */ -void setup_pm(device_t dev) +static void setup_pm(device_t dev) { - // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); @@ -216,7 +215,7 @@ static void vt8235_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -void vt8235_read_resources(device_t dev) +static void vt8235_read_resources(device_t dev) { struct resource *res; @@ -234,21 +233,20 @@ void vt8235_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -void vt8235_set_resources(device_t dev) +static void vt8235_set_resources(device_t dev) { - struct resource *resource; + //struct resource *resource; //resource = find_resource(dev,1); //resource->flags |= IORESOURCE_STORED; pci_dev_set_resources(dev); } -void vt8235_enable_resources(device_t dev) +static void vt8235_enable_resources(device_t dev) { /* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses) however it does control the isa bus and so we need to manually call enable childrens resources on that bus */ pci_dev_enable_resources(dev); enable_childrens_resources(dev); - } static void southbridge_init(struct device *dev) diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/vt8235_usb.c index 8b2a685807..c712136c72 100644 --- a/src/southbridge/via/vt8235/vt8235_usb.c +++ b/src/southbridge/via/vt8235/vt8235_usb.c @@ -27,7 +27,6 @@ static void usb_init(struct device *dev) */ } -/* static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -42,4 +41,4 @@ static const struct pci_driver northbridge_driver __pci_driver = { .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_82C586_2, }; -*/ + diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index f47c8c8dff..f7acb75766 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -65,7 +65,6 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; - u8 reg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ -- cgit v1.2.3