From e761b71e52e699abcfd22cc5e931b89cf354476e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 15 Jun 2013 12:29:23 +0300 Subject: bd82x6x: Fix early EHCI BAR programming MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change EHCI #2 to different BAR from EHCI #1. Even if the ECHI controllers are not to be addressed, it is bad idea to set two different devices to claim the same PCI memory cycles. Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3471 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/bd82x6x/early_usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index f4e526d85f..baf8c4fed7 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -49,9 +49,9 @@ void enable_usb_bar(void) cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd); - /* USB Controller 1 */ + /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); -- cgit v1.2.3